• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.3
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• pp.298-306
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• 2014

The railway signalling system for safe train operation regulates the train speed to ensure the safety distance between consecutive trains by using wayside facilities such as track circuits and interlocking systems. In addition, this signalling system controls the trackside equipment such as a railway point along the train line. This ground-equipment-based train control systems require high CAPEX and OPEX. To deal with these problems, the train control system using the on-board controller has been recently proposed and its related technologies have been widely studied. The on-board-controller-based train control system is that the on-board controller can directly control the trackside equipment on the train line. In addition, if this system is used, the wayside facilities can be simplified, and as a result, the efficient and cost-effective train control system can be realized. To this end, we have developed the prototypes of the on-board controller and wayside object control units which control the point and crossing gate and performed the integrated operation simulation in a testbed. In this paper, before the field test of the on-board-controller-based train control system, we perform the preliminary field trial including the installation test, wireless access test, interface test with other on-board devices, and normal operation test.

• The Transactions of the Korea Information Processing Society
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• v.4 no.7
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• pp.1821-1841
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• 1997

This paper presents an automated protocol conformance test sequence generation based on formal methods for LOTOS specification by using and applying many existing related algorithms and technique, such as the testing framework, Rural Chinese Postman tour concepts. We use the state-transition graphs obtained from LOTOS specifications by means of the CAESAR tool. This tool compiles a specification written in LOTOS into an extended Petri net, from which a transition graph of a event finite-state machine(EvFSM) including data is generated. A new characterizing sequence(CS), called Unique Event sequence(UE sequence) is defined. An UE sequence for a state is a sequence of accepted gate events that is unique for this state. Some experiences about UE sequence, partial UE sequence and signature are also explained. These sequences are combined with the concept of the Rural Chinese Postman Tour to obtain an optimal test sequence which is a minimum cost tour of the reference transition graph of the EvFSM. This paper also presents a fault coverage estimation experience of an automated method for optimized test sequences generation and the translation of the test sequence obtained by using our tool to TTCN notation are also given. A prototype of the proposed framework has been built with special attention to real application in order to generated the executable test cases in an automatic way. This formal method on conformance testing can be applied to the protocols related to IN, PCS and ATM for the purpose of verifying the correctness of implementation with respect to the given specification.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.430-439
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• 2004

This paper describes a design of 8192/2048-point FFT/IFFT processor (CFFT8k2k), which performs multi-carrier modulation/demodulation in OFDM-based DVB-T receiver. Since a large size FFT requires a large buffer memory, two design techniques are considered to achieve memory-efficient implementation of 8192-point FFT/IFFT. A hybrid structure, which is composed of radix-4 single-path delay feedback (R4SDF) and radix-4 single-path delay commutator (R4SDC), reduces its memory by 20% compared to R4SDC structure. In addition, a memory reduction of about 24% is achieved by a novel two-step convergent block floating-point scaling. As a result, it requires only 57% of memory used in conventional design, reducing chip area and power consumption. The CFFT8k2k core is designed in Verilog-HDL, and has about 102,000 Bates, RAM of 292k bits, and ROM of 39k bits. Using gate-level netlist with SDF which is synthesized using a $0.25-{\um}m$ CMOS library, timing simulation show that it can safely operate with 50-MHz clock at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. The functionality of the core is fully verified by FPGA implementation, and the average SQNR of 60-㏈ is achieved.