• Journal of Aerospace System Engineering
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• v.16 no.2
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• pp.13-24
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• 2022

As the scale of airborne system software increases, the use of OOT (Object-Oriented Technology) is increasing for functional expansion, efficient development, and code reuse, but the verification method for airborne object-oriented software is conducted from the perspective of the existing procedure-oriented program. The purpose of this paper was to analyze the characteristics of OOT and the vulnerabilities derived from the functional characteristics of OOT, and present a verification method applicable to each software development process (Design, Coding and Testing) to ensure the functional safety integrity of aviation software to which OOT is applied. Additionally, we analyzed the meaning of the static analysis results among the step-by-step verification measures proposed by applying LDRA, a static analysis automation tool, to PX4, an open source used to implement flight control software.

• Transactions of the Korean Society of Automotive Engineers
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• v.22 no.3
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• pp.68-74
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• 2014

As the number of ECUs (Electronic control units) are increasing, reliability and functional stability of a software in an ECU is getting more important. Therefore the application of functional safety standards ISO 26262 is making the software more reliable. Software fault injection test (SFIT) is required as a verification technique for the application of ISO 26262. In case of applying SFIT, an artificial error is injected to inspect the vulnerability of the system which is not easily detected during normal operation. In this paper, the basic concept of SFIT will be examined and the application of SIFT based on ISO26262 will be described.

• The KIPS Transactions:PartA
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• v.14A no.3 s.107
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• pp.141-146
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• 2007

In this paper, we proposed an efficient FPGA-based simulation acceleration method based on FPGA compilation avoidance, which can effectively decrease the long debugging turnaround time incurred from the every debugging process in the functional verification. The proposed method had been experimentally applied to the functional verification for a microcontroller design. It had clearly shown that the debugging turnaround time was greatly reduced while the high simulation speed of the simulation acceleration was still maintained.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.180-183
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• 2000

This paper presents a technique used for verifying the design of AE32000, a 32-bit microprocessor core. We follow the commonly used verification procedure while speeding up and completing the debugging process by adopting a reverse engineering scheme.

• Korean Journal of Computational Design and Engineering
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• v.5 no.4
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• pp.359-372
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• 2000

Current CAD systems are good enough to be used as a tool to manipulate three-dimensional shapes. This is a very important capability to be owned by a design tool because a major portion of designers'activities is spent on the shape manipulation in the design detailing process. However, the whole design process involves a lot more than the, shape manipulation. Currently, these remaining tasks, mostly logical reasoning process for the function realization together with structure decomposition in the top-down manner, are processed in the designer's brain. To support the top-down functional design process of a mechanical product, a system integrating the functional, structural and geometrical aspects of a product design in a unified environment is presented. Using this system, a designer can perform function decomposition, structure decomposition, and geometry detailing, and function verification activities in parallel and the whole design process it modeled resultantly. Once the whole design process is modeled, any redesign task can be automatically performed with the verification of the desired functions.

• IEMEK Journal of Embedded Systems and Applications
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• v.5 no.2
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• pp.67-76
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• 2010

Although both functional verification and performance evaluation are necessary for the development of effective and reliable communication systems, they have been often performed independently; by functional modeling with formal language tools and by performance modeling with professional network performance evaluation tools, respectively. Separate and repeated modeling of one system, however, would often result in cost increase and inconsistency between the models. This paper proposes an integrated model design approach in order to overcome this problem that evaluates the performance of a communication protocol designed in SDL with SDL-OPNET model conversion. The proposed technique generates OPNET skeleton code from Tau-generated C code of the SDL model by analyzing the relations between SDL and OPNET models. IEEE 802.2 LLC protocol was used as an example of model conversion to show the applicability and effectiveness of the proposed technique.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.83-88
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• 2007

In this paper, we propose the function verification method of the OLED(Organic Light Emitting Diode) drive IC using PLI verification method. This method uses the HDL(Hardware Description Language) simulator, PLI(Programing Language Interface), and GUI (Graphic User Interface) image viewer. This method improves the execute efficiency 40 times than conventional function verification methods. The proposed method can be used efficiently for function verification of DDI(display driver IC) design step.

• Journal of the Korea Society for Simulation
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• v.19 no.2
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• pp.157-164
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• 2010

While both functional verification and performance evaluation of a system are necessary for the development of effective and reliable communication systems, they have been usually performed individually through functional modeling with formal language tools and performance modeling with professional network performance evaluation tools, respectively. However, separate and duplicated modeling of a system may cause increase of the cost and inconsistency between the models. In order to overcome this problem, this paper proposes an integrated design technique that estimates the performance of a communication protocol designed in SDL with SDL-OPNET co-simulation. The proposed technique presents how to design a co-simulation system with the environment functions of Tau and the external system module of OPNET. InRes protocol was used as an example to show the applicability and usefulness of the proposed technique.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.4
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• pp.274-279
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• 2009

The flow of a universal system-level design methodology consists of system specification, system-level hardware/software partitioning, co-design, co-verification using virtual or physical prototype, and system integration. In this paper, verification environments based-on SystemVerilog and SystemC, one is native-code co-verification environment which makes prompt functional verification possible and another is SystemVerilog layered testbench which makes clock-level verification possible, are implemented. In native-code co-verification, HW and SW parts of SoC are respectively designed with SystemVerilog and SystemC after HW/SW partitioning using SystemC, then the functional interaction between HW and SW parts is carried out as one simulation process. SystemVerilog layered testbench is a verification environment including corner case test of DUT through the randomly generated test-vector. We adopt SystemC to design a component of verification environment which has multiple inheritance, and we combine SystemC design unit with the SystemVerilog layered testbench using SystemVerilog DPI and ModelSim macro. As multiple inheritance is useful for creating class types that combine the properties of two or more class types, the design of verification environment adopting SystemC in this paper can increase the code reusability.

• Journal of Internet Computing and Services
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• v.15 no.5
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• pp.107-121
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• 2014

Distributed systems are collection of physically distributed computers linked by a network. General use of wired/wireless Internet enables users to make use of distributed service anytime and anywhere. The explosive growth of distributed services strongly requires functional verification of services as well as verification of non-functional elements such as service quality. In order to verify distributed services it is necessary to build a test environment for distributed systems. Because, however, distributed systems are composed of physically distributed nodes, efforts to construct a test environment are required more than those in a test environment for a monolithic system. In this paper we propose a test framework to verify functional and non-functional features of distributed systems. The suggested framework automatically generates test cases through the message sequence charts, and includes a test driver composed of the virtual nodes which can simulate the physically distributed nodes. The test result can be checked easily through the various graphs and the graphical user interface (GUI). The test framework can reduce testing efforts for a distributed system and can enhance the reliability of the system.