• Proceedings of the KIEE Conference
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• 1997.07c
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• pp.948-950
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• 1997

This paper presents a basic interposing logic program to control nuclear power plant. In this paper we select a target control loop among the whole interposing modules, develop logic algorithm and functional software to compose target control loop. After that we carry out V&V(Verification and Validation) into the developed logic program to improve quality and reliability.

• Journal of Applied Reliability
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• v.13 no.1
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• pp.19-30
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• 2013

The requirements of reliability verification for new products and technology are increasing more and more in accordance with the trend change of strength for safety technology, functional skills and emotional quality. In order to conduct the purpose of robust design from the stage of product development recently, the application of reliability technology has gradually increased such as detecting the failure mode throughout the HALT technique, accelerated tests and so on. The main results are as follows; i) through the pre-test and analysis, detected the basic performance and predictable failure mode, ii) HALT technique and process has been developed that can be applied test methods for the next new products.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.9
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• pp.76-84
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• 1992

The DSP silicon compiler consists of language compiler, module generator, placement tool, router, layout generation tools, and simulator. In this paper, The language compiler, the module generator, placement tool, and simulator were developed and provided for the system designer. The language compiler translates the designer's system description language into the intermediate form file. The intermediate form file expresses the interconnections and specifications of the cells in the cell library. The simulator was developed and provided for the behavioral verification of the DSP system. For its implementation, the event-driven technique and the C$^{++}$ task library was used. The module generator was developed for the layout of the verified DSP system, and generates the functional block to be used in the DSP chip. And then the placement tool determines the appropriate positions of the cells in the DSP chip. In this paper, the placement tool was implemented by Min-Cut and Simulated Annealing algorithm. The placement process can be controlled by the several conditions input by the system designer.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.12
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• pp.9-19
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• 1997

This paper describes the design and FPGA implementation of a system control unit within a multiprocessor chip which can be used as a node processor ina massively parallel processing (MPP) caches, memory management units, a bus unit and a system control unit. Major functions of the system control unit are locking/unlocking of the shared variables of protected access, synchronization of instruction execution among four integer untis, control of interrupts, generation control of processor's status, etc. The system control unit was modeled in very high level using verilog HDL. Then, it was simulated and verified in an environment where trap handler and external interrupt controller were added. Functional blocks of the system control unit were changed into RTL(register transfer level) model and synthesized using xilinx FPGA cell library in synopsys tool. The synthesized system control unit was implemented by Xilinx FPGA chip (XC4025EPG299) after timing verification.

• Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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• 2002.10a
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• pp.186-190
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• 2002

In this paper, various kinds of A-Frame are surveyed and classified according to their functional ability and sizes. Based on the study, a A-Frame that is suitable for ROV/AUV operation is designed. Basic theoretical structural requirements are applied and relevant Finite Element Analysis are earned out for the verification of the sound workability of the proposed A-Frame. Final configuration and the specification are proposed for the usage of ROV/AUV operation.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.50 no.1
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• pp.45-50
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• 2001

With increasing complexity of digital logic circuits, fast and accurate verification of functional behaviour becomes most critical bottleneck in meeting time-to-market requirement. This paper presents several techniques for accelerating a cycle-based logic simulation. The acceleration techniques include parallel pattern logic evaluation, circuit size reduction, and the partition of feedback loops in sequential circuits. Among all, the circuit size reduction plays a critical role in maximizing logic simulation speedup by reducing 50% of entire circuit nodes on the average. These techniques are incorporated into a levelized table-driven logic simulation system rather than a compiled-code simulation algorithm. Finally, experimental results are given to demonstrate the effectiveness of the proposed acceleration techniques. Experimental results show more than 27 times performance improvement over single pattern levelized logic simulation.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.959-961
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• 2003

In this paper, we describe implemented DMAC (Direct Memory Access Controller) architecture on Altera's $Excalibur^{TM}$ that includes industry-standard $ARM922T^{TM}$ 32-bit RISC processor core operating at 200 MHz. We implemented DMAC based on AMBA (Advanced Micro-controller Bus Architecture) AHB (Advanced Micro-performance Bus) interface. Implemented DMAC has 8-channel and can extend supportable channel count according to user application. We used round-robin method for priority selection. Implemented DMAC supports data transfer between Memory-to-Memory, Memory-to-Peripheral and Peripheral-to-Memory. The max transfer count is 1024 per a time and it can support byte, half-word and word transfer according to AHB protocol (HSIZE signals). We implemented with VHDL and functional verification using $ModelSim^{TM}$. Then, we synthesized using $LeonardoSpectrum^{TM}$ with Altera $Excalibur^{TM}$ library. We did FPGA P&R and targeting using $Quartus^{TM}$. We can use implemented DMAC module at any system that needs high speed and broad bandwidth data transfers.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.29 no.4 s.235
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• pp.526-536
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• 2005

A heat dissipation modeling method of EEE parts, or semi-empirical heat dissipation method, is developed for thermal design and analysis an electronic equipment of geostationary satellite. The power consumption measurement value of each functional breadboard is used for the heat dissipation modeling method. For the purpose of conduction heat transfer modeling of EEE parts, surface heat model using very thin ignorable thermal plates is developed instead of conventional lumped capacity nodes. The thermal plates are projected to the printed circuit board and can be modeled and modified easily by numerically preprocessing programs according to design changes. These modeling methods are applied to the thermal design and analysis of CTU (Command and Telemetry Unit) and verified by thermal cycling and vacuum tests.

• Journal of TMJ Balancing Medicine
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• v.11 no.1
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• pp.25-36
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• 2021

It was observed that the effectiveness of Yin-yang balancing therapy of the tempromandibular joint (YBT) or functional cerebrospinal therapy (FCS) in three cases: an acute and a chronic motor tic disorder and a Tourrette's disorder (TD). These three cases were mainly managed with cervical balancing appliance for the Yin-yang Balancing on tempromandibular joint (TMJ) and pelvic balance therapy. They were treated concurrently with acupuncture, cupping and herb-medicine. Clinical outcome measurement was based on subjective measures with visual analogue scale (VAS), Yale Global Tic Severity Scale (YGTTS) and clinical observations for 235, 279 and 273 days respectively. The patient showed positive changes after the treatment and this effect maintained over the follow-up period. Although it is not clear whether the effect is sustained afterwards or not, a positive effect on the motor tic disorders and TD was observed. And so, furthermore strict clinical and structural researches for verification on YBT is expected.

• Journal of Food Hygiene and Safety
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• v.39 no.2
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• pp.61-71
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• 2024

In this study, we analyzed chlorogenic acid indicator components in preparation for the additional listing of green coffee bean extract in the Health Functional Food Code and optimized caffeine for simultaneous analysis. We extracted chlorogenic acid and caffeine using 30% methanol, phosphoric acid solution, and acetonitrile-containing phosphoric acid and analyzed them at 330 and 280 nm, respectively, using liquid chromatography. Our analysis validation results yielded a correlation coefficient (R²) revealing a significance level of at least 0.999 within the linear quantitative range. The chlorogenic acid and caffeine detection and quantification limits were 0.5 and 0.2 ㎍/mL and 1.4, and 0.4 ㎍/mL, respectively. We confirmed that the precision and accuracy results were suitable using the AOAC validation guidelines. Finally, we developed a simultaneous chlorogenic acid and caffeine analysis approach. In addition, we confirmed that our analysis approach could simultaneously quantify chlorogenic acid and caffeine by examining the applicability of each formulation through prototypes and distribution products. In conclusion, the results of this study demonstrated that the standardized analysis would expectably increase chlorogenic acidcontaining health functional food quality control reliability.