• Journal of Korea Multimedia Society
• /
• v.13 no.7
• /
• pp.943-949
• /
• 2010

This paper presents some improvements on VLSI implementation of lifting-based 9/7 wavelet transform by optimization hardware multiplication. The proposed solution requires less logic area and power consumption without performance loss compared to previous wavelet filter structure based on lifting scheme. This paper proposes a better approach to the hardware implementation using Lefevre algorithm based on extensions of Pattern search methods. To compare the proposed structure to the previous solutions on full multiplier blocks, we implemented them using Verilog HDL. For a hardware implementation of the two solutions, the logical synthesis on 0.18 um standard cells technology show that area, maximum delay and power consumption of the proposed architecture can be reduced up to 51%, 43% and 30%, respectively, compared to previous solutions for a 200 MHz target clock frequency. Our evaluation show that when design VLSI chip of lifting-based 9/7 wavelet filter, our solution is better suited for standard-cell application-specific integrated circuits than prior works on complete multiplier blocks.

• Journal of Korean Society of Archives and Records Management
• /
• v.9 no.2
• /
• pp.59-78
• /
• 2009

In this study, considering the importance of the providing archival information services over the Web in university archives, the evaluation model of the archival information services was proposed by identifying categories and contents of it. Direction for the improvement was proposed by evaluating and analyzing the Web archival information services of some university archives in Korea. Based on the evaluation, the following directions for improvement were suggested. First, the mission and vision of the archives should be established and published over the Web. Second, the introduction to the records catalogues and records collection should be provided in detail on the Web. Third, advanced search and full-text search functions should be provided, as well as the help information for the search methods. Fourth, university archives' Web sites should provide online exhibitions and newsletters of the archives.

• Journal of Korean Academy of Nursing
• /
• v.45 no.5
• /
• pp.627-640
• /
• 2015

Purpose: The objective of this systematic review was to assess the effects of family support programs on caregiving burden, depression, and stress in family caregivers of people with dementia. Methods: A literature search was conducted of electronic databases to identify randomized controlled studies with family support programs done between 2000 and 2014. Studies published in English and/or Korean were included for the analysis with search strategies adapted from the Cochrane Dementia and Cognitive Improvement Group. Studies were rated for quality assessment by two independent reviewers using the appraisal checklist developed by Cochrane Reviews and Dissemination. Of 8,334 articles identified in the literature search, full texts of 76 articles that met the inclusion criteria were reviewed and 38 were found to include relevant outcomes. Results: Results from selected studies were pooled in statistical meta-analysis using Review Manager Software and heterogeneity between combined studies was assessed using the Chi-square test. Meta-analysis showed that the effect sizes of family caregiver support programs were small to medium for categories of caregiving burden (Hedge's g= - 0.17, 95% CI= - 0.30~ - 0.04), depression (Hedge's g= - 0.30, 95% CI= - 0.40~ - 0.20), and stress (Hedge's g= - 0.39, 95% CI= - 0.52~ - 0.25). Conclusion: The review results indicate that a support programs can assist family caregivers in reducing their psycho-emotional distress.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.5 no.1
• /
• pp.23-30
• /
• 2010

The H.264/AVC is increasingly used in broadcast video applications such as Internet Protocol television (IPTV), digital multimedia broadcasting (DMB) because of high compression performance. But the H.264/AVC coded video can be delivered to the widespread end-user equipment for MPEG-2 after transcoding between this video standards. This paper suggests a new transcoding algorithm for H.264/AVC to MPEG-2 transcoder that uses motion vector clustering in order to reduce the complexity without loss of video quality. The proposed method is exploiting the motion information gathered during h.264 decoding stage. To reduce the search space for the MPEG-2 motion estimation, the predictive motion vector is selected with a least distortion of the candidated motion vectors. These candidate motion vectors are considering the correlation of direction and distance of motion vectors of variable blocks in H.264/AVC. And then the best predictive motion vector is refined with full-search in ${\pm}2$ pixel search area. Compared with a cascaded decoder-encoder, the proposed transcoder achieves computational complexity savings up to 64% with a similar PSNR at the constant bitrate(CBR).

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.1C
• /
• pp.69-77
• /
• 2002

Sine digital signal processing for motion pictures requires huge amount of data computation to store, manipulate and transmit, more effective data compression is necessary. Therefore, the ITU-T recommended H.26x as data compression standards for digital motion pictures. The data compression method that eliminates time redundancies by motion estimation using relationship between picture frames has been widely used. Most video conding systems employ block matching algorithm for the motion estimation and compensation, and the algorithm is based on the minimun value of cast functions. Therefore, fast search algorithm rather than full search algorithm is more effective in real time low data rates encodings such as H.26x. In this paper, motion estimation employing the Nearest-Neighbors algorithm is designed to reduce search time using FPGA, coded in VHDL, and simulated and verified using Xilink Foundation.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.34 no.3C
• /
• pp.288-296
• /
• 2009

In POCS (projection onto convex sets)-based reconstruction of HR (high resolution) image, the quality of reconstructed image is gradually improved through iterative motion estimation and image restoration. The amount of computation, however, increases because of the repeated inter-frame motion estimation. In this paper, an HR reconstruction algorithm is proposed where modified ARPS (adaptive rood pattern search) and POCS are simultaneously performed. In the modified ARPS, the motion estimates obtained from phase correlation or from the previous steps in POCS restoration are utilized as the initial reference in the motion estimation. Moreover, estimated motion is regularized with reference to the neighboring blocks' motion to enhance the reliability. Computer simulation results show that, when compared to conventional methods which are composed of full search block matching and POCS restoration, the proposed method is about 30 times faster and yet produces HR images of almost equal or better quality.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.4A
• /
• pp.364-370
• /
• 2002

In this paper, we propose a VLSI array architecture for high speed processing of FBMA. First of all, the sequential FBMA is transformed into a single assignment code by using the index space expansion, and then the dependance graph is obtained from it. The two dimensional VLSI array is derived by projecting the dependance graph along the optimal direction. Since the candidate blocks in the search range are overlapped with columns as well as rows, the processing elements of the VLSI array are designed to reuse the overlapped data. As the results, the number of data inputs is reduced so that the processing performance is improved. The proposed VLSI array has (N$^2$+1)${\times}$(2p+1) processing elements and (N+2p) input ports where N is the block size and p is the maximum search range. The computation time of the rat reference block is (N$^2$+2(p+1)N+6p), and the block pipeline period is (3N+4p-1).

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.48 no.1
• /
• pp.64-70
• /
• 2011

In an H.264/AVC video encoder, the motion estimation at fractional pixel accuracy improves a coding efficiency and image quality. However, it requires additional computation overheads for fractional search and interpolation, and thus, reducing the computation complexity of fractional search becomes more important. This paper proposes a Pixel Re-composition Fractional Motion Estimation (PRFME) algorithm for an H.264/AVC video encoder. Fractional Motion Estimation performs interpolation for the overlapped pixels which increases the computational complexity. PRFME can reduce the computational complexity by eliminating the overlapped pixel interpolation. Compared with the fast full search, the proposed algorithm can reduce 18.1% of computational complexity, meanwhile, the maximum PSNR degradation is less than 0.067dB. Therefore, the proposed PRFME algorithm is quite suitable for mobile applications requiring low power and complexity.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.12
• /
• pp.58-65
• /
• 2011

This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs, such as H.264/AVC, MPEG4, etc. With the proposed specific instructions and variable point 2D SAD hardware accelerator, it can handle the real-time processing requirement of High Definition (HD) video. With the SAD unit and its parallel operations using pattern information, the proposed IME instructions support not only full search algorithms but also other fast search algorithms. The hardware size is 25.5K gates for each Processing Element Group (PEG) which has 128 SAD Processor Elements (PEs). The proposed ASIP has been verified by the Synopsys Processor Designer and implemented by the Design Compiler using the IBM 90nm process technology. The hardware size is 453K gates for the IME unit and the operating frequency is 188MHz for 1080p@30 frame in real time. The proposed ASIP can reduce the hardware size about 26% and the number of operation cycles about 18%.

• Journal of Digital Contents Society
• /
• v.15 no.5
• /
• pp.651-661
• /
• 2014

The complexity to search a specific content over TV platform is drastically increasing. Based on previous studies from computer data management system, we propose a new method that helps users to search and select content effectively. In general, contents over computers are represented by spatial metaphor, which replicates our physical environment and value systems about space. We suggest 3D lattice structure to construct information space for TV platform. Users can infer relevance between contents via special clue in information space, so as to select content more easily. Also, they can search contents through its temporal property that also represented in space. We make full use of our natural capability that can reduce additional overload to learning new interface. The results of this study can be significant and heuristic contributions, as they can be applied to diverse service areas utilizing video contents.