• The Journal of the Acoustical Society of Korea
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• v.13 no.2E
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• pp.20-25
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• 1994

The major drawback to the Code Excited Linear Prediction(CELP) type vocoders is their large computational requirements. In this paper, a simple method is proposed to reduce the pitch searching time in the pitch filter almost without degradation of quality. Bease upon the observational regularity of the correlation function of speech, the searching range can be restricted to the positive side in pitch search. This is done by skipping the negative side with the width which is estimated from the previous positive envelope. In addition to that, the maximum number of available lags can be limited by the threshold, $L_T$, which is set on 58 empirically. So, only the limited numbers of lags are considered in pitch search, which is less than a half of that of the full search method. By using the proposed method in pitch search, its required computations are greatly reduced. Experimental result shows 51% time reduction almost without lowering the speech quality in segmental SNR measure.

• Journal of the Korea Computer Industry Society
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• v.3 no.7
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• pp.927-936
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• 2002

This paper presents the extraction of a feature by motion vector for efficient content-based retrieval for digital video. in this paper, divided by general size block for the current frame by video, using BMA(block matching algorithm) for an estimate by block move based on a time frame. but in case BMA appeared on a different pattern fact of motion in the vector obtain for the BMA. solve in this a problem to application for full search method this method is detected by of on many calculations. I propose an alternative plan in this paper Limit the search region to $\pm$15 and search is a limit integer pixel. a result, in this paper is make an estimate motion vector in more accurately using motion vector in adjoin in blocks. however, refer to the block vector because occurrence synchronism. Such addition information is get hold burden receive to transmit therefore, forecasted that motion feature each block and consider for problems for establish search region. in this paper Algorithm based to an examination Motion Estimation method by for motion Compensation is proposed.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.2
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• pp.126-131
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• 2004

Full search algorithm(FA) provides the best performance but this is usually impractical because of the large number of computations required for large search region. Fast search and conventional Boolean matching algorithms reduce computational complexity and data processing time but this algorithms have disadvantages that is difficult of implementation of hardware because of high control overhead and that is less performance than FA. This paper presents new Boolean matching algorithm, called BCBM(Bit Converted Boolean Matching). Proposed algorithm has performance closed to the FA by Boolean only block matching that may be very efficiently implemented in hardware for real time video communication. Simulation results show that the PSNR of the proposed algorithm is about 0.08㏈ loss than FA but is about 0.96∼2.02㏈ gain than fast search algorithm and conventional Boolean matching algorithm.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.1
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• pp.402-410
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• 2013

In this paper, we propose a new fast block matching algorithm for block matching using the temporal and spatially correlation of the video sequence and local statistics of neighboring motion vectors. Since the temporal correlation of the video sequence between the motion vector of current block and the motion vector of previous block. The proposed algorithm determines the location of a better starting point for the search of an exact motion vector using the point of the smallest SAD(sum of absolute difference) value by the predicted motion vectors of neighboring blocks around the same block of the previous frame and the current frame and the predictor candidate point on each division region by binary-tree structure. Experimental results show that the proposed algorithm has the capability to dramatically reduce the search points and computing cost for motion estimation, comparing to fast FS(full search) motion estimation and other fast motion estimation.

• Journal of the Korean BIBLIA Society for library and Information Science
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• v.20 no.4
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• pp.67-84
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• 2009

Cyber Textbook Museum is created by the Korean Educational Development Institute in part of the project to manage the knowledge and information of Korea to promote understanding of Korean education and its history. The original and full text of textbooks dating from the 1890s to the present have been digitized and arranged for easy access over internet. An exclusive portal site dealing with Korean textbooks and curriculum materials was made to provide not only the directory service of textbooks and curriculums in diverse data classifications, school levels, years/periods and subjects but also the keyword search by searching engine. Users can search the necessary materials easily and systematically over the screen and use all the functions except save, capture and print. The management system for textbook image(DjVu format), search system and DRM(Digital Rights Management) system were developed. Finally, four suggestions are proposed which are related in the aspects of policy, technical, systematic aspects for active and tremendous use of the site.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.5
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• pp.509-517
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• 2001

Full-search algorithm requires large amount of computation which causes time delay or very complex hardware architecture for real time implementation. In this paper, we propose a fast motion estimator based on bit-plane matching, which reduce the computational complexity and the hardware cost. In the proposed motion estimator, the conventional motion estimation algorithms are applied to the binary images directly extracted from the video sequence. Furthermore, in the proposed VLSI motion estimator, we employ a Pair of processing cores that calculate the motion vector continuously By controlling the data flow in a systolic fashion using the internal shift registers in the processing cores, we avoid using SRAM (local memory) so that we remove the time overhead for accessing the local memory and adopt lower-cost fabrication technology. We modeled and tested the proposed motion estimator in VHDL, and then synthesized the whole system which has been integrated in a 0.6-$\mu$m triple-metal CMOS chip of size 8.15 X 10.84$\textrm{mm}^2$.

• Journal of Broadcast Engineering
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• v.23 no.5
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• pp.628-635
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• 2018

In this paper, we propose a fast motion estimation algorithm which is important in video encoding. So many fast motion estimation algorithms have been published for improving prediction quality and computational reduction. In the paper, we propose an algorithm that reduces unnecessary computation, while almost keeping prediction quality compared with the full search algorithm. The proposed algorithm calculates the sum of partial block matching error for each candidate, selects the candidates for the next step, compares the stability of optimal candidates with minimum error, and finds optimal motion vectors by determining the progress of the next step. By doing that, we can find the minimum error point as soon as possible and obtain fast computational speed by reducing unnecessary computations. Additionally, the proposed algorithm can be used with conventional fast motion estimation algorithms and prove it in the experimental results.

• Journal of Broadcast Engineering
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• v.8 no.3
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• pp.288-296
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• 2003

ATSC (Advanced Television System Committee) has specified 18 video formats for DTV (Digital Television), e.g., scan format, size format, and frame rate format conversion. Effective MPEG-2 video transcoders should support any conversion between the above-mentioned formats. Scan format conversion Is hard to Implement because it may often induce frame rate and size format conversion together. Especially. because of picture type conversion caused by scan format conversion, the computational burden of motion estimation (ME) in transcoding becomes serious. This paper proposes a fast ME algorithm for MPEG-2 video transcoding supporting scan format conversion. Firstly, we extract and compose a set of candidate motion vectors (MVs) from the input bit-stream to comply with the re-encoding format. Secondly, the best MV is chosen among several candidate MVs by using a weighted median selector. Simulation results show that the proposed ME algorithm provides outstanding PSNR performance close to full search ME, while reducing the transcoding complexity significantly.

• The KIPS Transactions:PartB
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• v.8B no.5
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• pp.557-564
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• 2001

In general, several moving regions with different motions coexist in a block located on motion boundaries in the block-based motion estimation. In this case the motion compensation error(MCEs) are different with the moving regions. This is inclined to deteriorate the quality of motion compensated images because of the inaccurate motions estimated from the conventional mean absolute error(MAE) based matching function in which the matching error per pixel is accumulate throughout the block. In this paper, we divided a block into the regions according to their motions using the motion information of the spatio-temporally neighboring blocks and calculate the average MCF for each moving mentioned. From the simulation results, we showed the improved performance of the proposed method by comparing the results from other methods such as the full search method and the edge oriented block matching algorithm. Especially, we improved the quality of the motion compensated images of blocks on motion boundaries.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.85-92
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• 2009

This paper proposes a full-search block-matching motion estimation circuit with hybrid architecture combining systolic arrays and adder trees for an MPEG-4 encoder. The proposed circuit uses systolic arrays for motion estimation with a small number of clock cycles and adder trees to reduce required circuit resources. The interpolation circuit for 1/2 pixel motion estimation consists of six adders, four subtracters and ten registers. We improved the circuit performance by resource sharing and efficient scheduling techniques. We described the motion estimation circuit for integer and 1/2 pixels at RTL in Verilog HDL. The logic-level circuit synthesized by using 130nm standard cell library contains 218,257 gates and can process 94 D1($720{\times}480$) image frames per second.