• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.7 no.1
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• pp.41-58
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• 2007

A compact and broadband $4{\times}1$ array antenna was developed for 3G smart antenna system testbed. The $4{\times}1$ uniform linear array antenna was designed to operate at 1.885 to 2.2GHz with a total bandwidth of 315MHz. The array elements were based on the novel broadband L-probe fed inverted hybrid E-H (LIEH) shaped microstrip patch, which offers 22% size reduction to the conventional rectangular microstrip patch antenna. For steering the antenna beam, a commercial variable attenuator (KAT1D04SA002), a variable phase shifter (KPH350SC00) with four units each, and the corporate 4-ways Wilkinson power divider which was fabricated in-house were integrated to form the beamforming feed network. The developed antenna has an impedance bandwidth of 17.32% ($VSWR{\leq}1.5$), 21.78% ($VSWR{\leq}2$) with respect to center frequency 2.02GHz and with an achievable gain of 11.9dBi. The design antenna offer a broadband, compact and mobile solution for a 3G smart antenna testbed to fully characterized the IMT-2000 radio specifications and system performances.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.2
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• pp.56-62
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• 1999

This paper described a voice dialing system(VDS) and its hardware implementation for a speaker-dependent recognition of Korean digit speech using duty cycle. The proposed VDS consist of integrator, leveling divider circuit and recognition program. The analog speech signal is applied to the VDS through the low-pass filter cutoff frequency is 4.5(kHz). It is thoroughly confirmed that the speaker-dependent recognition of Korean digit speech is well behaved by the hardware system. Experimental results show that the recognition rate is 64% in average for Korean digit speech. Moreover, a high recognition rate of 100% is obtained for digits; /4/, /5/, /6/, /7/, /9/, /0/.

• ETRI Journal
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• v.40 no.5
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• pp.664-676
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• 2018

Given the rapidly increasing market penetration of photovoltaic (PV) systems in many fields, including construction and housing, the effective maintenance of PV systems through remote monitoring at the panel level has attracted attention to quickly detect faults that cause reductions in yearly PV energy production, and which can reduce the whole-life cost. A key point of PV monitoring at the panel level is cost-effectiveness, as the installation of the massive PV panels that comprise PV systems is showing rapid growth in the market. This paper proposes an implementation method that involves the use of a panel-level wireless PV monitoring module (WPMM), and which assesses the cost-effectiveness of this approach. To maximize the cost-effectiveness, the designed WPMM uses a voltage-divider scheme for voltage metering and a shunt-resistor scheme for current metering. In addition, the proposed method offsets the effect of element errors by extracting calibration parameters. Furthermore, a design method is presented for portable and user-friendly PV monitoring, and demonstration results using a commercial 30-kW PV system are described.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3181-3183
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• 1999

A CMOS two-stage oscillator applicable to requiring in- and quadrature-phase components such as RF and data retiming applications are presented using phase-look-ahead technique. This paper clearly describes the operation principle of the presented two-stage oscillator and the principle can be also applicable to the high speed high speed divide-by-two is usually used for prescaler of the frequency synthesizer. Also, the sucessful oscillation of the proposed oscillator using PLA is confirmed through the experiment. The test vehicle is designed using 0.8 ${\mu}m$ N-well CMOS process and it has a maximum 914MHz oscillation showing -75dBclHz phase noise at 100kHz offset with single 2V supply.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.675-677
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• 2009

통신기기에서 중요한 기술 중 하나인 PLL(Phase Locked Loop) 회로는 주기적인 신호를 원하는 대로, 정확한 고정점으로 잡아주는데 그 목적을 둔다. 일반적인 구조로 위상주파수검출기(Phase Frequency detector), 루프필터(Loop filter), 전압제어발진기(Voltage Controlled Oscillator), 디바이더(Divider)로 구성되어진다. 그러나 일반적인 PLL 구조로는 지터(jitter)가 증가하고 트랙(tracking) 속도가 느리다는 단점이 있다. 이를 보완하기 위해 루프필터 전단에 차지펌프(Charge pump) 회로를 추가하여 사용하고 있다. 본 논문에서는 CMOS를 이용한 PLL용 차지펌프를 설계하였다. 설계된 회로는 $0.18{\mu}m$ CMOS 공정 기술을 사용하여 CADENCE사의 Specter로 시뮬레이션 하였으며, Virtuso2로 레이아웃 하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.40-49
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• 2008

A Frequency synthesizer for mobile-DTV applications is implemented using $0.18{\mu}m$ CMOS process with 1.8V supply. PMOS transistors are chosen for VCO core to reduce phase noise. The measurement result of VCO frequency range is 800MHz-1.67GHz using switchable inductors, capacitors and varactors. We use varactor bias technique for the improvement of VCO gain linearity, and the number of varactor biasing are minimized as two. VCO gain deterioration is also improved by using the varactor switching technique. The VCO gain and interval of VCO gain are maintained as low and improved using the VCO frequency calibration block. The sigma-delta modulator for fractional divider is designed by the co-simualtion method for accuracy and efficiency improvement. The VCO, PFD, CP and LF are verified by Cadence Spectre, and the sigma-delta modulator is simulated using Matlab Simulink, ModelSim and HSPICE. The power consumption of the frequency synthesizer is 18mW, and the VCO has 52.1% tuning range according to the VCO maximum output frequency. The VCO phase noise is lower than -100dBc/Hz at 1MHz at 1MHz offset for 1GHz, 1.5GHz, and 2GHz output frequencies.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.5
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• pp.444-449
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• 2009

This paper presents the design of a dual band branch line hybrid coupler(BLHC) with different power division ratios at two bands. In the proposed design, transmission lines of the BLHC are transformed to $\pi$-type equivalent circuits which represent different impedances and $\lambda/4$ electrical length at two frequency bands. In order to verify the proposed method, a dual band coupler with different power division ratios is designed for 0.9 GHz and 2 GHz applications. The desired power division ratios are 1:1 and 1:3 at the two operating frequency bands. The measured results show excellent performance with an insertion loss of less than 0.33 dB, a return loss of less than -18.07 dB, and good isolation characteristics.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.7
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• pp.1267-1275
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• 2017

This paper describes a design of cryptographic processor supporting 233-bit elliptic curves over binary field defined by NIST. Scalar point multiplication that is core arithmetic in elliptic curve cryptography(ECC) was implemented by adopting modified Montgomery ladder algorithm, making it robust against simple power analysis attack. Point addition and point doubling operations on elliptic curve were implemented by finite field multiplication, squaring, and division operations over $GF(2^{233})$, which is based on affine coordinates. Finite field multiplier and divider were implemented by applying shift-and-add algorithm and extended Euclidean algorithm, respectively, resulting in reduced gate counts. The ECC processor was verified by FPGA implementation using Virtex5 device. The ECC processor synthesized using a 0.18 um CMOS cell library occupies 49,271 gate equivalents (GEs), and the estimated maximum clock frequency is 345 MHz. One scalar point multiplication takes 490,699 clock cycles, and the computation time is 1.4 msec at the maximum clock frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.9
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• pp.967-973
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• 2009

In this paper, X-band satellite communication oscillator of double phase locked is implemented by constructing a couple of phased-locked loop, and then we have analyzed the phase noise of designed PLL-DRO. The designed phase-locked oscillator is consist of series feedback DRO, frequency divider, phase detector, loop filter and programmable PLL-IC. By dividing oscillation frequency of 12.6 GHz into two frequencies, it exhibits output power of 15.32 dBm at 6.3 GHz. Phase noises of implemented oscillator are -81 dBc/Hz@100Hz, -100.86 dBc/Hz@1 kHz, -111.12 dBc/Hz@10 kHz, -116 dBc/Hz@100 kHz and -140.49 dBc/Hz@1 MHz respectively. These indicate excellent stable operation of oscillator and very good phase noise characteristics.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.1 s.92
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• pp.49-55
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• 2005

In this paper, the phase locked harmonic oscillator(PLHO) using the analog PLL(Phase Locked Loop) is designed and implemented for a wireless LAN system. The harmonic oscillator is consisted of a ring resonator, a varactor diode and a PLL circuit. Because the fundamental fiequency of 8.5 GHz is used as the feedback signal for the PLL and the 2nd harmonic of 17.0 GHz is used as the output, a analog frequency divider for the phase comparison in the PLL system can be omitted. For the simple PLL circuit, the SPD(Sampling Phase Detector) as a phase comparator is used. The output power of the phase locked harmonic oscillator is 2.23 dBm at 17 GHz. The fundamental and 3rd harmonic suppressions are -31.5 dBc and -29.0 dBc, respectively. The measured phase noise characteristics are -87.6 dBc/Hz and -95.4 dBc/Hz at the of offset frequency of 1 kHz and 10 kHz from the carrier, respectively.