• Title/Summary/Keyword: Fourth Generation Mobile Communication

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Optimal Node Analysis in LoRaWAN Class B (LoRaWAN Class B에서의 최적 노드 분석)

  • Seo, Eui-seong;Jang, Jong-wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2019.05a
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    • pp.100-103
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    • 2019
  • Due to the fourth industrial revolution called 'fusion and connection', interest in 'high connectivity society' and 'highland society' is increasing, and related objects are not limited to automation and connected cars. The Internet of Things is the main concern of the 4th Industrial Revolution and it is expected to play an important role in establishing the basis of the next generation mobile communication service. Several domestic and foreign companies have been studying various types of LPWANs for the construction of the Internet based on things, and there is Semtech's LoRaWAN technology as representative. LoRaWAN is a long-distance, low-power network designed to manage a large number of devices and sensors, with communications from hundreds to thousands to thousands of devices and sensors. In this paper, we analyze the optimum node capacity of gateway for maximum performance while reducing resource waste in using LoRaWAN.

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A 14b 100MS/s $3.4mm^2$ 145mW 0.18um CMOS Pipeline A/D Converter (14b 100MS/s $3.4mm^2$ 145mW 0.18un CMOS 파이프라인 A/D 변환기)

  • Kim Young-Ju;Park Yong-Hyun;Yoo Si-Wook;Kim Yong-Woo;Lee Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.5 s.347
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    • pp.54-63
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    • 2006
  • This work proposes a 14b 100MS/s 0.18um CMOS ADC with optimized resolution, conversion speed, die area, and power dissipation to obtain the performance required in the fourth-generation mobile communication systems. The 3-stage pipeline ADC, whose optimized architecture is analyzed and verified with behavioral model simulations, employs a wide-band low-noise SHA to achieve a 14b level ENOB at the Nyquist input frequency, 3-D fully symmetric layout techniques to minimize capacitor mismatch in two MDACs, and a back-end 6b flash ADC based on open-loop offset sampling and interpolation to obtain 6b accuracy and small chip area at 100MS/s. The prototype ADC implemented in a 0.18um CMOS process shows the measured DNL and INL of maximum 1.03LSB and 5.47LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 59dB and 72dB, respectively, and a power consumption of 145mW at 100MS/s and 1.8V. The occupied active die area is $3.4mm^2$.