• Journal of KIISE:Information Networking
• /
• v.30 no.6
• /
• pp.755-763
• /
• 2003

To improve performance over noisy wireless channels, mobile wireless networks employ forward error correction(FEC) techniques. The performance of static FEC algorithms, however, degrades by poorly matching the overhead of their correction code to the degree of the fluctuating underlying channel error. This paper proposes an adaptive FEC technique called FECA(FEC-level Adaptation), which dynamically tunes FEC strength to the currently estimated channel error rate at the data link layer. FECA is suitable for wireless networks whose error rate is high and slowly changing compared to the round-trip time between two communicating nodes. One such example network would be a sensor network in which the average bit error rate is higher than $10^{-6}$ and the detected error rate at one time lasts a few hundred milliseconds on average. Our experiments show that FECA performs 15% in simulations with theoretically modeled wireless channels and in trace-driven simulations based on the data collected from real sensor networks better than any other static FEC algorithms.

• Journal of Broadcast Engineering
• /
• v.19 no.2
• /
• pp.268-271
• /
• 2014

Conventional forward error correction (FEC) code rate decision schemes using analytical source coding distortion model and channel-induced distortion model are usually complex, and require the typical process of model parameter training which involves potentially high computational complexity and implementation cost. To avoid the complex modeling procedure, we propose a simple but accurate joint source-channel distortion model to estimate channel loss threshold set for optimal FEC code rate decision.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2010.10a
• /
• pp.162-164
• /
• 2010

Terrestrial trunked radio (TETRA) standard specifies shortened Reed-Muller (RM) codes as forward error correction means for control signals. In this paper, we compare decoding algorithms for RM codes in TETRA, in terms of performance and complexity trade-off. Belief propagation and majority logic decoding algorithms are selected for comparison.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.12C
• /
• pp.1633-1641
• /
• 2004

In satellite digital broadcasting and satellite internet, severe burst errors occur in the high-speed return channel from the satellite to mobiles. In this paper, we analyze the performance of the forward error correction (FEC) coding method in the Rayleigh fading return channel. We first investigate the channel model of Loo, LutB, Vucetic and Corazza. We then compare the performance of the convolutional, Reed-Solomon (RS), convolution-RS concatenation, and Turbo codes in rayleigh fading channel.

• Journal of information and communication convergence engineering
• /
• v.14 no.4
• /
• pp.240-245
• /
• 2016

Scalable video streaming over wireless networks has many challenges. The most significant challenge is related to packet loss. To overcome this problem, in this paper, we propose an unequal loss protection (ULP) method using a new forward error correction (FEC) mechanism for robust scalable video streaming over wireless networks. For an efficient FEC assignment considering video quality, we first introduce a simple and efficient performance metric, the layer-based recovery rate (LRR), for quantifying the unequal error propagation effects of the temporal and quality layers on the basis of packet losses. LRR is based on the unequal importance in both the temporal and the quality layers of a hierarchical scalable video coding structure. Then, the proposed ULP-LRR method assigns an appropriate number of FEC packets on the basis of the LRR to protect the video layers against packet lossy network environments. Compared with conventional ULP algorithms, the proposed ULP-LRR algorithm demonstrates a higher performance for various error-prone wireless channel statuses.

• Journal of Communications and Networks
• /
• v.9 no.3
• /
• pp.265-273
• /
• 2007

This paper expands an analytical performance model of 802.11 to accurately estimate throughput and energy demand of 802.11-based wireless sensor network (WSN) when sensor nodes employ Reed-Solomon (RS) codes, one of block forward error correction (FEC) techniques. This model evaluates these two metrics as a function of the channel bit error rate (BER) and the RS symbol size. Since the basic recovery unit of RS codes is a symbol not a bit, the symbol size affects the WSN performance even if each packet carries the same amount of FEC check bits. The larger size is more effective to recover long-lasting error bursts although it increases the computational complexity of encoding and decoding RS codes. For applying the extended model to WSNs, this paper collects traffic traces from a WSN consisting of two TIP50CM sensor nodes and measures its energy consumption for processing RS codes. Based on traces, it approximates WSN channels with Gilbert models. The computational analyses confirm that the adoption of RS codes in 802.11 significantly improves its throughput and energy efficiency of WSNs with a high BER. They also predict that the choice of an appropriate RS symbol size causes a lot of difference in throughput and power waste over short-term durations while the symbol size rarely affects the long-term average of these metrics.

• Proceedings of the IEEK Conference
• /
• 2000.06a
• /
• pp.9-12
• /
• 2000

A forward error correction (FEC) is usually used to correct the errors of the real-time data occurred at the reciever side which require a real-time transmission. The data transmission is peformed after being encapsulating by RTP and UDP. In the ITU-T study group 16, four FEC schemes using the XORing are presented. In the paper, a new supplementary scheme is proposed. In the delay problem the new scheme performs better than the scheme 3 but in the recovery ability for successive packet loss is worse than scheme 3. The proposed scheme which supplements the present schemes can be adapted easily to the current network environment.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.5
• /
• pp.465-472
• /
• 2013

This paper presents a low-complexity triple-error-correcting parallel Bose-Chaudhuri-Hocquenghem (BCH) decoder architecture and its efficient design techniques. A novel modified step-by-step (m-SBS) decoding algorithm, which significantly reduces computational complexity, is proposed for the parallel BCH decoder. In addition, a determinant calculator and a error locator are proposed to reduce hardware complexity. Specifically, a sharing syndrome factor calculator and a self-error detection scheme are proposed. The multi-channel multi-parallel BCH decoder using the proposed m-SBS algorithm and design techniques have considerably less hardware complexity and latency than those using a conventional algorithms. For a 16-channel 4-parallel (1020, 990) BCH decoder over GF($2^{12}$), the proposed design can lead to a reduction in complexity of at least 23 % compared to conventional architecttures.

• 제어로봇시스템학회:학술대회논문집
• /
• 1996.10b
• /
• pp.28-31
• /
• 1996

We propose an estimator design method of Stewart platform, which gives the 6DOF, positions and velcities of Stewart platform from the measured cylinder length. The solution of forward kinematics is not solved yet as a useful realtime application tool because of the complexity of the equation with multiple solutions. Hence we suggest an nonlinear estimator for the forward kinematics solution using Luenberger observer with nonlinear error correction term. But the way of residual gain selection of the estimator is not clear, so we suggest an algebraic Riccati equation for gain matrix using Lyapunov method. This algorithm gives the sufficient condition of the stability of error dynamics and can be extended to general nonlinear system.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.7
• /
• pp.140-148
• /
• 2013

This paper presents a iterative Bose-Chaudhuri-hocquenghem (i-BCH) code and its high-speed decoder architecture for 100 Gb/s optical communications. The proposed architecture features a very high data processing rate as well as excellent error correction capability. The proposed 6-iteration i-BCH code structure with interleaving method allows the decoder to achieve 9.34 dB net coding gain performance at $10^{-15}$ decoder output bit error rate to compensate for serious transmission quality degradation. The proposed high-speed i-BCH decoder architecture is synthesized using a 90-nm CMOS technology. It can operate at a clock frequency of 430 MHz and achieve a data processing rate of 100 Gb/s. Thus, it has potential applications in next generation forward error correction (FEC) schemes for 100 Gb/s optical communications.