• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.679-682
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• 1998

This paper presents the VLSI implementation of RS(reed-solomon) decoder using the Modified Euclidean Algorithm(hereafter MEA) for DVD(Digital Versatile Disc) and CD(Compact Disc). The decoder has a capability of correcting 8-error or 16-erasure for DVD and 2-error or 4-erasure for CD. The technique of polynomial evaluation is introduced to realize syndrome calculation and a polynomial expansion circuit is developed to calculate the Forney syndrome polynomial and the erasure locator polynomial. Due to the property of our system with buffer memory, the MEA architecture can have a recursive structure which the number of basic operating cells can be reduced to one. We also proposed five criteria to determine an uncorrectable codeword in using the MEA. The overall architecture is a simple and regular and has a 4-stage pipelined structure.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권3호
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• pp.193-202
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• 2010

This paper presents a high-speed low-complexity pipelined Reed-Solomon (RS) (255,239) decoder using pipelined reformulated inversionless Berlekamp-Massey (pRiBM) algorithm and its folded version (PF-RiBM). Also, this paper offers efficient pipelining and folding technique of the RS decoders. This architecture uses pipelined Galois-Field (GF) multipliers in the syndrome computation block, key equation solver (KES) block, Forney block, Chien search block and error correction block to enhance the clock frequency. A high-speed pipelined RS decoder based on the pRiBM algorithm and its folded version have been designed and implemented with 90-nm CMOS technology in a supply voltage of 1.1 V. The proposed RS(255,239) decoder operates at a clock frequency of 700 MHz using the pRiBM architecture and also operates at a clock frequency of 750 MHz using the PF-RiBM, respectively. The proposed architectures feature high clock frequency and low-complexity.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2005년도 종합학술발표회 논문집 Vol.15 No.1
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• pp.131-136
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• 2005

UWB is the most spotlighted wireless technology that transmits data at very high rates using low power over a wide spectrum of frequency band. UWB technology makes it possible to transmit data at rate over 100Mbps within 10 meters. To preserve important header information, MB-OFDM UWB adopts Reed-Solomon(23,17) code. In receiver, RS decoder needs high speed and low latency using efficient hardware. In this paper, we suggest the architecture of RS decoder for MB-OFDM UWB. We adopts Modified-Euclidean algorithm for key equation solver block which is most complex in area. We suggest pipelined processing cell for this block and show the detailed architecture of syndrome, Chien search and Forney algorithm block. At last, we show the hardware implementation results of RS decoder for ASIC implementation.

• 한국정보기술응용학회:학술대회논문집
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• 한국정보기술응용학회 2005년도 6th 2005 International Conference on Computers, Communications and System
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• pp.195-198
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• 2005

UWB is the most spotlighted wireless technology that transmits data at very high rates using low power over a wide spectrum of frequency band. UWB technology makes it possible to transmit data at rate over 100Mbps within 10 meters. To preserve important header information, MBOFDM UWB adopts Reed-Solomon(23,17) code. In receiver, RS decoder needs high speed and low latency using efficient hardware. In this paper, we suggest the architecture of RS decoder for MBOFDM UWB. We adopts Modified-Euclidean algorithm for key equation solver block which is most complex in area. We suggest pipelined processing cell for this block and show the detailed architecture of syndrome, Chien search and Forney algorithm block. At last, we show the hardware implementation results of RS decoder for ASIC implementation.

• 대한전기학회논문지:전력기술부문A
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• 제48권7호
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• pp.909-915
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• 1999

In this paper, we propose an efficient VLSI architecture of Reed-Solomon(RS) decoder. To improve the speed. we develope an architecture featuring parallel and pipelined processing. To implement the parallel and pipelined processing architecture, we analyze the RS decoding algorithm and the honor's algorithm for parallel processing and we also modified the Euclid's algorithm to apply the efficient parallel structure in RS decoder. To show the proposed architecture, the performance of the proposed RS decoder is compared to Shao's and we obtain the 10 % efficiency in area and three times faster in speed when it's compared to Shao's time domain decoder. In addition, we implemented the proposed RS decoder with Altera FPGA Flex10K-50.

• 한국정보통신학회논문지
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• 제8권1호
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• pp.170-178
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• 2004

본 논문에서는 Modified Euclid 알고리즘을 이용하여 고속의 Reed-Solomon 복호기를 설계하였다. Reed-Solomon 부호의 복호 알고리즘은 오증을 계산하고, 에러 위치 다항식을 구한 후, 에러를 판단하여, 에러 크기 값을 구하는 4단계로 이루어지는데, 본 논문에서는 복호기의 속도를 증가시키고 Latency를 줄이기 위하여 병렬구조의 신드롬 생성기와 빠른 클록 속도의 Modified Euclid 알고리즘 블록을 사용하였으며, Chien Search 블록에서는 에러 위치 다항식을 짝수항과 홀수항으로 나누어 설계하였다. 먼저, 알고리즘과 회로의 동작을 확인하기 위해 C++로 프로그램을 작성하여 검증을 한 후, 이를 바탕으로 Verilog로 하드웨어를 기술하였다. 또한, 각 블록에 대한 로직 시뮬레이션을 거친 후, $.25{\mu}m$ CMOS 라이브러리를 이용하여 Synopsys사의 합성 툴로 합성을 하고, 최종적으로 후반부 설계인 레이아웃을 시행하였다. 본 논문의 칩은 최대 동작 주파수가 250MHz로서 최대 데이터 전송률은 1Gbps이다.