• Journal of the Microelectronics and Packaging Society
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• v.7 no.2
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• pp.55-62
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• 2000

The wetting balance test was performed in an attempt to estimate the wetting properties of the UBM-coated Si-wafer on one side to the Sn-Pb solder. The wetting curves of the one and both side-coated UBM layers had the similar shape and the parameters characterizing the curve shape showed the similar transition tendency to the temperature. The wetting property estimation was possible with the new wettability indices from the wetting curves of one side-coated specimen; $F_{min}$, $F_{s}t_{s}$ and $t_s$. For UBM of Si-chip, Au/Cu/Cr UBM was better than Au/Ni/Ti in the point of wetting time. The contact angle of the one side coated Si-plate to the Sn-Pb solder could be calculated from the force balance equation by measuring the static state force and the tilt angle.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.366-369
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• 2003

The vertical fountain plating system with the point contact has been used in semiconductor industry. But the plating shape in the opening of photoresist becomes gradated shape, because bubbles from the wafer surface are difficult to escape from the deep openings, vias. So, we designed the tilted electrode ring contact to get uniform bump height on all over the wafer and evaluated the film uniformity by SEM and $\alpha$-step. A photoresist was coated to a thickness of $60{\mu}m$ and vias were patterned by a contact aligner After via opening, solder layer was electroplated using the fountain plating system and the tilted electrode ring contact system. In $\alpha$-step measurement, film uniformities in the fountain plating system and the tilted electrode ring contact system were ${\pm}16%,\;{\pm}3.7%$ respectively. In this study, we could get high uniformity bumps by the tilted electrode ring contact system. So, tilted electrode ring contact system is expected to improve workability and yield in module process.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.49 no.3
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• pp.31-37
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• 2012

This paper presents an efficient hardware architecture to enable the high-speed Givens rotation-based QR decomposition. The proposed architecture achieves a highly parallel givens rotation process by maximizing the number of pivots selected for parallel zero-insertions. Sign-select lookahed (SSL)-CORDIC is also efficiently used for the high-speed givens rotation. The performance of QR decomposition hardware considerably increases compared to the conventional triangular systolic array (TSA) architecture. Moreover, the circuit area of QR decomposition hardware was reduced by decreasing the number of flip-flops for holding the pre-computed results during the decomposition process. The proposed QR decomposition hardware was implemented using TSMC $0.25{\mu}m$ technology. The experimental results show that the proposed architecture achieves up to 70 % speed-up over the TACR/TSA-based architecture for the $8{\times}8$ matrix decomposition.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.2 s.39
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• pp.21-26
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• 2006

We developed a bonding at low temperature using fine pitch Sn and In bumps, and studied the reliability of the fine pitch In-Sn solder joints. The $30{\mu}m$ pitch Sn and In bumps were joined together at $120^{\circ}C$. A non conductive adhesive (NCA) was applied during solder joining. Thermal cycling test ($0^{\circ}C-100^{\circ}C$, 2 cycles/h) of up to 2000 cycles was carried out to evaluate the reliability of the solder joints. The bondability was evaluated by measuring the contact resistance (Rc) of the joints through the four point probe method. As the content of filler increased, the reliability improved in the solder joints during thermal cycling test because the contact resistance increased little. The filler redistributed the stress and strains from the thermal shock over the entire joint area.

• Journal of Biosystems Engineering
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• v.12 no.1
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• pp.45-52
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• 1987

In order to improve the thermal efficiency of an internal combustion engine, various ignition timing control systems were examined and the best one was chosen. The parts used for the systems were a microcomputer system with DAS, 8 bit output port (D-FLIP FLOP), three types of isolation circuit, two types of ignition timing pulse generator, three types of switching circuit and two types of high voltage ignition circuit. Most systems did not operate well due to the effects of electromagnetic waves and surge currents occurring when the ignition began or ended with resulting high voltage. The best ignition timing control system was found to be the combination of (microcomputer system)-(ignition timing pulse generator using step motor position control pick-up)-(switching circuit using TR logic)-(high voltage ignition circuit using CDI).

• Journal of the Institute of Convergence Signal Processing
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• v.21 no.4
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• pp.183-194
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• 2020

Recently, the number of hip dysplasia (DDH) that occurs during infant and child growth has been increasing. DDH should be detected and treated as early as possible because it hinders infant growth and causes many other side effects In this study, two modelling techniques were used for multiple training techniques. Based on the results after the first transformation, the training was designed to be possible even with a small amount of data. The vertical flip, rotation, width and height shift functions were used to improve the efficiency of the model. Adam optimization was applied for parameter learning with the learning parameter initially set at 2.0 x 10e-4. Training was stopped when the validation loss was at the minimum. respectively A novel image overlay system using 3D laser scanner and a non-rigid registration method is implemented and its accuracy is evaluated. By using the proposed system, we successfully related the preoperative images with an open organ in the operating room

• Korean Journal of Radiology
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• v.21 no.4
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• pp.483-493
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• 2020

Objective: To evaluate the distribution and characteristics of peripheral nerve abnormalities in chronic inflammatory demyelinating polyneuropathy (CIDP) using magnetic resonance neurography (MRN) and to examine the diagnostic efficiency. Materials and Methods: Thirty-one CIDP patients and 21 controls underwent MR scans. Three-dimensional sampling perfections with application-optimized contrasts using different flip-angle evolutions and T1-/T2- weighted turbo spin-echo sequences were performed for neurography of the brachial and lumbosacral (LS) plexus and cauda equina, respectively. Clinical data and scores of the inflammatory Rasch-built overall disability scale (I-RODS) in CIDP were obtained. Results: The bilateral extracranial vagus (n = 11), trigeminal (n = 12), and intercostal nerves (n = 10) were hypertrophic. Plexus hypertrophies were observed in the brachial plexus of 19 patients (61.3%) and in the LS plexus of 25 patients (80.6%). Patterns of hypertrophy included uniform hypertrophy (17 [54.8%] brachial plexuses and 21 [67.7%] LS plexuses), and multifocal fusiform hypertrophy (2 [6.5%] brachial plexuses and 4 [12.9%] LS plexuses) was present. Enlarged and/or contrast-enhanced cauda equina was found in 3 (9.7%) and 13 (41.9%) patients, respectively. Diameters of the brachial and LS nerve roots were significantly larger in CIDP than in controls (p < 0.001). The largest AUC was obtained for the L5 nerve. There were no significant differences in the course duration, I-RODS score, or diameter between patients with and without hypertrophy. Conclusion: MRN is useful for the assessment of distribution and characteristics of the peripheral nerves in CIDP. Compared to other regions, LS plexus neurography is more sensitive for CIDP.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.27-38
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• 2016

This work proposes a 12b 30MS/s 0.18um CMOS SAR ADC based on low-power composite switching with an active die area of $0.16mm^2$. The proposed composite switching employs the conventional $V_{CM}$-based switching and monotonic switching sequences while minimizing the switching power consumption of a DAC and the dynamic offset to constrain a linearity of the SAR ADC. Two equally-divided capacitors topology and the reference scaling are employed to implement the $V_{CM}$-based switching effectively and match an input signal range with a reference voltage range in the proposed C-R hybrid DAC. The techniques also simplify the overall circuits and reduce the total number of unit capacitors up to 64 in the fully differential version of the prototype 12b ADC. Meanwhile, the SAR logic block of the proposed SAR ADC employs a simple latch-type register rather than a D flip-flop-based register not only to improve the speed and stability of the SAR operation but also to reduce the area and power consumption by driving reference switches in the DAC directly without any decoder. The measured DNL and INL of the prototype ADC in a 0.18um CMOS are within 0.85LSB and 2.53LSB, respectively. The ADC shows a maximum SNDR of a 59.33dB and a maximum SFDR of 69.83dB at 30MS/s. The ADC consumes 2.25mW at a 1.8V supply voltage.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.3
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• pp.29-35
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• 2003

The Sn-based lead-free solders with varying microstructure were prepared by changing the cooling rate from the melt. Bulky as-cast SnAg, SnAgCu, and SnCu, alloys were cold rolled and thermally stabilized before the creep tests so that there would be very small amount of microstructural change during creep (TS), and thin specimens were water quenched from the melt (WQ) to simulate microstructures of the as-reflowed solders in flip chips. Cooling rates of the WQ specimens were 140∼150 K/sec, and the resultant $\beta-Sn$ globule size was 5∼10 times smaller than that of the TS specimens. Subsequent creep tests showed that the minimum strain rate of TS specimens was about $10_2$ times higher than that of the WQ specimens. Fractographic analyses showed that creep rupture of the TS-SnAgCu specimens occurred by the nucleation of voids on the $Ag_3Sn$ Sn or $Cu_6Sn_5$ particles in the matrix, their subsequent growth by the power-law creep, and inter-linkage of microcracks to form macrocracks which led to the fast failure. On the other hand, no creep voids were found in the WQ specimens due to the mode III shear rupture coming from the thin specimens geometry.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.4
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• pp.60-70
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• 2000

An 8$\times$8+20-bit MAC is designed with low power design methodologies at each of the system design levels. At algorithm level, a new method for multipl $y_tract operation is proposed, and it saves the transistor counts over conventional methods in hardware realization. A new Booth selector circuit using NMOS pass-transistor logic is also proposed at circuit level. It is superior to other circuits designed by CMOS in power-delay-product. And at architecture level, we adopted an ELM adder that is known to be the most efficient in power consumption, operating frequency, area and design regularity as the final adder. For registers, dynamic CMOS single-edge triggered flip-flops are used because they need less transistors per bit. To increase the operating frequency 2-stage pipeline architecture is adopted, and fast 4：2 compressors are applied in Wallace tree block. As a simulation result, the designed MAC in 0.6${\mu}{\textrm}{m}$ 1-poly 3-metal CMOS process is operated at 200MHz, 3.3V and consumed 35㎽ of power in multiply operation, and operated at 100MHz consuming 29㎽ in MAC operations, respectively.ly.