• Title/Summary/Keyword: Flip Chip Bump

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Studies on the Interfacial Reaction between Electroless-Plated UBM (Under Bump Metallurgy) on Cu pads and Pb-Sn-Ag Solder Bumps (Cu pad위에 무전해 도금된 UBM (Under Bump Metallurgy)과 Pb-Sn-Ag 솔더 범프 계면 반응에 관한 연구)

  • Na, Jae-Ung;Baek, Gyeong-Uk
    • Korean Journal of Materials Research
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    • v.10 no.12
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    • pp.853-863
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    • 2000
  • In this study, a new UBM materials system for solder flip chip interconnection of Cu pads were investigated using electroless copper (E-Cu) and electroless nickel (E-Ni) plating method. The interfacial reaction between several UBM structures and Sn-36Pb-2Ag solder and its effect on solder bump joint mechanical reliability were investigated to optimife the UBM materials design for solder bump on Cu pads. Fer the E-Cu UBM, continuous coarse scallop-like $Cu_{6}$ $Sn_{5}$ , intermetallic compound (IMC) was formed at the solder/E-Cu interface, and bump fracture occurred this interface under relative small load. In contrast, Fer the E-Ni/E-Cu UBM, it was observed that E-Ni effectively limited the growth of IMC at the interface, and the Polygonal $Ni_3$$Sn_4$ IMC was formed because of crystallographic mismatch between monoclinic $Ni_3$$Sn_4$ and amorphous E-Ni phase. Consequently, relatively higher bump adhesion strength was observed at E-Ni/E-Cu UBM than E-Cu UBM. As a result, it was fecund that E-Ni/E-Cu UBM material system was a better choice for solder flip chip interconnection on CU PadS.

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Interconnection Process and Electrical Properties of the Interconnection Joints for 3D Stack Package with $75{\mu}m$ Cu Via ($75{\mu}m$ Cu via가 형성된 3D 스택 패키지용 interconnection 공정 및 접합부의 전기적 특성)

  • Lee Kwang-Yong;Oh Teck-Su;Won Hye-Jin;Lee Jae-Ho;Oh Tae-Sung
    • Journal of the Microelectronics and Packaging Society
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    • v.12 no.2 s.35
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    • pp.111-119
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    • 2005
  • Stack specimen with three dimensional interconnection structure through Cu via of $75{\mu}m$ diameter, $90{\mu}m$ height and $150{\mu}m$ pitch was successfully fabricated using subsequent processes of via hole formation with Deep RIE (reactive ion etching), Cu via filling with pulse-reverse electroplating, Si thinning with CMP, photolithography, metal film sputtering, Cu/Sn bump formation, and flip chip bonding. Contact resistance of Cu/Sn bump and Cu via resistance could be determined ken the slope of the daisy chain resistance vs the number of bump joints of the flip chip specimen containing Cu via. When flip- chip bonded at $270^{\circ}C$ for 2 minutes, the contact resistance of the Cu/Sn bump joints of $100{\times}100{\mu}m$ size was 6.7m$\Omega$ and the Cu via resistance of $75{\mu}m$ diameter, $90{\mu}m$ height was 2.3m$\Omega$.

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Analysis of thermal characteristic variations in LD arrays packaged by flip-chip solder-bump bonding technique (플립 칩 본딩으로 패키징한 레이저 다이오우드 어레이의 열적 특성 변화 분석)

  • 서종화;정종민;지윤규
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.3
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    • pp.140-151
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    • 1996
  • In this paper, we analyze the variations of thermal characteristics of LD (laser diode) arrays packaged by a flip-chip bonding method. When we simulate the temperature distribution in LD arrays with a BEM (boundary element method) program coded in this paper, we find that thermal crosstalks in LD arrays packaged by the flip-chip bonding method increases by 250-340% compared to that in LD arrays packaged by previous methods. In the LD array module packaged by the flip-chip bonding technique without TEC (thermo-electric cooler), the important parameter is the absolute temperature of the active layer increased due cooler), the important parameter is the absolute temperature of th eactiv elayers of LD arrays to thermal crosstalk. And we find that the temperature of the active layers of LD arrays increases up to 125$^{\circ}C$ whenall four LDs, without a carefully designed heatsink, are turned on, assuming the power consumption of 100mW from each LD. In order to reduce thermal crosstalk we propose a heatsink sturcture which can decrease the temeprature at the active layer by 40%.

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Effect of the Tolerance Parameters of the Horn on the Vibration of the Thermosonic Transverse Bonding Flip Chip System (횡 방향 플립 칩 초음파 접합 시 혼의 공차변수가 시스템의 진동에 미치는 영향)

  • Jung, Ha-Kyu;Kwon, Won-Tae;Yoon, Byung-Ok
    • Transactions of the Korean Society of Machine Tool Engineers
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    • v.18 no.1
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    • pp.116-121
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    • 2009
  • Thermosonic flip chip bonding is an important technology for the electronic packaging due to its simplicity, cost effectiveness and clean and dry process. Mechanical properties of the horn and the shank, such as the natural frequency and the amplitude, have a great effect on the bonding capability of the transverse flip chip bonding system. In this research, two kinds of study are performed. The first is the new design of the clamp and the second is the effect of tolerance parameters to the performance of the system. The clamp with a bent shape is newly designed to hold the nodal point of the flip chip. The second is the effect of the design parameters on the vibration amplitude and planarity at the end of the shank. The variation of the tolerance parameters changes the amplitude and the frequency of the vibration of the shank. They, in turn, have an effect on the quantity of the plastic deformation of the gold ball bump, which determined the quality of the flip chip bonding. The tolerance parameters that give the great effect on the amplitude of the shank are determined using Taguchi's method. Error of set-up angle, the length and diameter of horn and error of the length of the shank are determined to be the parameters that have peat effect on the amplitude of the system.

Studies on Copper Pillar Bump with Trapezoidal Cross Section on the Top Surface for Reliability Improvement (사다리꼴 상부 단면을 갖는 구리기둥 범프의 신뢰성 향상에 대한 연구)

  • Cho, Il-Hwan
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.25 no.7
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    • pp.496-499
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    • 2012
  • Modified structure of copper pillar bump which has trapezoidal cross section on the top region is suggested with simulation results and concept of fabrication process. Due to the large surface area of joint region between bump and solder in suggested structure, electro-migration effect can be reduced. Reduction of electro-migration is related with current density and joule heating in bump and investigated with finite element methods with variation of dimensional parameters. Mechanical characteristics are also investigated with comparing modified copper pillar bump and conventional copper pillar bump.

Effect of Under Bump Metallization (UBM) on Interfacial Reaction and Shear Strength of Electroplated Pure Tin Solder Bump (전해 도금된 주석 솔더 범프의 계면 반응과 전단 강도에 미치는 UBM의 효과)

  • Kim, Yu-Na;Koo, Ja-Myeong;Park, Sun-Kyu;Jung, Seung-Boo
    • Korean Journal of Metals and Materials
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    • v.46 no.1
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    • pp.33-38
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    • 2008
  • The interfacial reactions and shear strength of pure Sn solder bump were investigated with different under bump metallizations (UBMs) and reflow numbers. Two different UBMs were employed in this study: Cu and Ni. Cu6Sn5 and Cu3Sn intermetallic compounds (IMCs) were formed at the bump/Cu UBM interface, whereas only a Ni3Sn4 IMC was formed at the bump/Ni UBM interface. These IMCs grew with increasing reflow number. The growth of the Cu-Sn IMCs was faster than that of the Ni-Sn IMC. These interfacial reactions greatly affected the shear properties of the bumps.

Studies on the Interfacial Reaction between electroplated Eutectic Pb/Sn Flip-Chip Solder Bump and UBM(Under Bump Metallurgy) (전해 도금법을 이용한 공정 납-주석 플립 칩 솔더 범프와 UBM(Under Bump Metallurgy) 계면반응에 관한 연구)

  • Jang, Se-Yeong;Baek, Gyeong-Ok
    • Korean Journal of Materials Research
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    • v.9 no.3
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    • pp.288-294
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    • 1999
  • In the flip chip interconnection using solder bump, the Under Bump Metallurgy (UBM) is required to perform multiple functions in its conversion of an aluminum bond pad to a solderable surface. In this study, various UBM systems such as $Al 1\mu\textrm{m} / Ti 0.2\mu\textrm{m} / Cu 5\mu\textrm{m}, Al 1\mu\textrm{m} / Ti 0.2\mu\textrm{m} / Cu 1\mu\textrm{m}, al 1\mu\textrm{m}/Ni 0.2\mu\textrm{m} / Cu 1\mu\textrm{m} and Al 1\mu\textrm{m}/Pd 0.2\mu\textrm{m} / Cu 1\mu\textrm{m}$ for flip chip interconnection using the low melting point eutectic 63Sn-37Pb solder were investigated and compared to their metallurgical properties. $100\mu\textrm{m}$ size bumps were prepared for using an electroplating process. The effects of the number of reflows and aging time on the growth of intermetallic compounds(IMC) were investigated. $Cu_6Sn_5$ and $Cu_3Sn$ IMC were abserved after aging treatment in the UBM system with thick coper $(Al 1\mu\textrm{m}/Ti 0.2\mu\textrm{m}/Cu 5\mu\textrm{m})$. However only the $Cu_6Sn_5$ was detected in the UBM system with $1\mu\textrm{m}$ thick copper even after 2 reflow and 7 day aging at $150^{\circ}C$. Complete Cu consumption by Cu-Sn IMC growth gives rise to a direct contact between solder inner layer such as Ti, Ni and Pd, and hence to possibly cause reactions between two of them. In this study, however, only for the Pd case, IMC of PdSn. was observed by Cu consumption. UBM interfacial reactions with s이der affected the adhesion strength ot s이der balls after s이der reflow and annealing treatment.

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Recent Advances in Fine Pitch Cu Pillar Bumps for Advanced Semiconductor Packaging (첨단 반도체 패키징을 위한 미세 피치 Cu Pillar Bump 연구 동향)

  • Eun-Chae Noh;Hyo-Won Lee;Jeong-Won Yoon
    • Journal of the Microelectronics and Packaging Society
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    • v.30 no.3
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    • pp.1-10
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    • 2023
  • Recently, as the demand for high-performance computers and mobile products increases, semiconductor packages are becoming high-integration and high-density. Therefore, in order to transmit a large amount of data at once, micro bumps such as flip-chip and Cu pillar that can reduce bump size and pitch and increase I/O density are used. However, when the size of the bumps is smaller than 70 ㎛, the brittleness increases and electrical properties decrease due to the rapid increase of the IMC volume fraction in the solder joint, which deteriorates the reliability of the solder joint. Therefore, in order to improve these issues, a layer that serves to prevent diffusion is inserted between the UBM (Under Bump Metallization) or pillar and the solder cap. In this review paper, various studies to improve bonding properties by suppressing excessive IMC growth of micro-bumps through additional layer insertion were compared and analyzed.

Aging Characteristic of Shear Strength in Micro Solder Bump (마이크로 솔더 범프의 전단강도와 시효 특성)

  • 김경섭;유정희;선용빈
    • Journal of Welding and Joining
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    • v.20 no.5
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    • pp.72-77
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    • 2002
  • Flip-chip interconnection that uses solder bump is an essential technology to improve the performance of microelectronics which require higher working speed, higher density, and smaller size. In this paper, the shear strength of Cr/Cr-Cu/Cu UBM structure of the high-melting solder b01p and that of low-melting solder bump after aging is evaluated. Observe intermetallic compound and bump joint condition at the interface between solder and UBM by SEM and TEM. And analyze the shear load concentrated to bump applying finite element analysis. As a result of experiment, the maximum shear strength of Sn-97wt%Pb which was treated 900 hrs aging has been decreased as 25% and Sn-37wt%Pb sample has been decreased as 20%. By the aging process, the growth of $Cu_6Sn_5$ and $Cu_3Sn$ is ascertained. And the tendency of crack path movement that is interior of a solder to intermetallic compound interface is found.

Via-size Dependance of Solder Bump Formation (비아 크기가 솔더범프 형성에 미치는 영향)

  • 김성진;주철원;박성수;백규하;이상균;송민규
    • Journal of the Microelectronics and Packaging Society
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    • v.8 no.1
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    • pp.33-38
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    • 2001
  • We investigate the via-size dependance of as-electroplated- and reflow-bump shapes for realizing both high-density and high-aspect ratio of solder bump. The solder bump is fabricated by subsequent processes as follows. After sputtering a TiW/Al electrode on a 5-inch Si-wafer, a thick photoresist for via formation it obtained by multiple-codling method and then vias with various diameters are defined by a conventional photolithography technique using a contact alinger with an I-line source. After via formation the under ball metallurgy (UBM) structure with Ti-adhesion and Cu-seed layers is sputtered on a sample. Cu-layer and Sn/pb-layer with a competition ratio of 6 to 4 are electroplated by a selective electroplating method. The reflow-bump diameters at bottom are unchanged, compared with as-electroplated diameters. As-electroplated- and reflow-bump shapes, however, depend significantly on the via size. The heights of as-electroplated and reflow bumps increase with the larger cia, while the aspect ratio of bump decreases. The nearest bumps may be touched by decreasing the bump pitch in order to obtain high-density bump. The touching between the nearest bumps occurs during the overplating procedure rather than the reflowing procedure because the mushroom diameter formed by overplating is larger than the reflow-bump diameter. The arrangement as zig-zag rows can be effective for realizing the flip-chip-interconnect bump with both high-density and high-aspect ratio.

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