• Proceedings of the Korean Society of Computer Information Conference
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• 2016.07a
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• pp.319-320
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• 2016

본 논문에서는 게임 개발에 있어서 빈번하게 적용되고 있는 식물 생태계와 이와 연동하는 동물 생태계를 자동화 하는 기법을 연구하고, 이를 실제로 구현하는 것을 목적으로 한다. 정해진 몇 가지 변수에 의해 자동 생성된 식물 생태계와 추가적인 FSM을 기반으로 생성되는 동물 생태계의 자동 생성 로직을 설계하고 이를 구현함으로써 기존의 게임 개발 과정에 효율성을 증대시키고, 최근 들어 터레인의 동적인 구성이나 유저와의 다양한 상호작용으로 인하여 빈번하게 요구되고 있는 자동화된 생태계 생성 기능을 구현하여 게임의 다양성이 기여하고자 한다. 본 논문에서 연구된 연구 결과는 추후에 일반적인 온라인 게임의 배경 자동 생성 시스템으로 확장되어 보다 다양한 적용이 가능할 것이다.

• The Transactions of the Korea Information Processing Society
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• v.4 no.8
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• pp.2152-2162
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• 1997

We developed an approach to automatically synthesize time-stationary controllers for a given pipelined data path of Application Specific Integrated Circuits (ASICs). This work consists of automated production of control specifications and Finite State Machine (FSM) Optimization. A FSM controller is implemented by performing horizontal partitioning so as to minimize the total controller area. We compared our approach to published work on FSM generation and optimization, and the results indicate large savings in total controller area.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2006.05a
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• pp.317-321
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• 2006

게임의 재미요소를 증대 시키고, 게임 생명주기(Life-Cycle)를 늘어나게 하기 위해 다양한 방법이 연구 중이다. 현실감 있는 그래픽 효과와 뛰어난 음향 효과 등과 함께 게임 플레이어의 게임 스타일이 반영된 게임을 만들기 위한 방법이 대표적이 예라 할 수 있다. 그 중 게임 플레이어의 스타일을 게임에 다시 이용하기 위해서는 플레이어의 인지과정이 요구되며, 인지된 결과를 이용하여 플레이어를 모델링(User Modeling)한다. 하지만, 게임의 종류와 특성에 따라 다양한 게임이 존재하기 때문에 플레이어를 모델링하기 어렵다는 문제를 가지고 있다. 본 논문에서는 게임에서 정의된 FSM(Finite State machine)을 이용하여 플레이어가 선택한 행동 패턴을 분석하고 적용하는 방법과 다양한 게임에서 이용 할 수 있는 스크립트 형태의 NPC 행동 패턴 변경 방법을 제안한다. 플레이어의 데이터를 분석하여 얻은 결과는 FSM을 변경하여 새로운 행동을 보이는 NPC(Non-Player Characters)를 생성하는데 사용되며, 이 캐릭터는 게임의 특성과 플레이어의 최신 행동 패턴 경향을 학습한 적용형 NPC라 할 수 있다. 실험을 통하여 사용자의 행동과 유사한 패턴을 보이는 NPC의 생성을 확인할 수 있었으며, 게임에서 상대적인 또는 적대적인 캐릭터로 유용하게 사용 될 수 있다.

• Journal of Korea Game Society
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• v.14 no.5
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• pp.127-136
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• 2014

NPC in game is an important factor to increase the fun of the game by cooperating with player or confrontation with player. NPC's behavior patterns in the previous games are limited. Also, there is not much difference in NPC's ability among the existing games because it's designed to FSM. Therefore, players who have matched with NPCs which have the characteristics may have difficulty to play. This paper is for improving the problem and production and evaluation of the game NPC behavior model based on wolves hunting model in real life. To achieve it, first, the research surveys and studies behavior states for wolves to capture prey in the real world. Secondly, it is implemented using the Unity3D engine. Third, this paper compares the implemented state transition probability to state transition probability in real world, state transition probability in general game. The comparison shows that the number of state transitions of NPCs increases, proportions of implemented NPC behavior patterns converges to probabilities of state transition in real-world. This means that the aggressive behavior pattern of NPC implemented is similar to the wolf hunting behavior pattern of the real world, and it can thereby provide more player experience.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.358-362
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• 2004

Verification and testing are complementary techniques that are used to increase the level of confidence in the correct functioning of communication systems as prescribed by their specifications. This paper presents an experience of model checking for a formal railway signaling protocol specified in LTS (Labeled Transition System). This formal approach checks deadlock, livelock and reachability for the state and action to verify whether properties expressed in modal logic are true on specifications. We also propose a formal method for semi-automated test case generation for a railway signaling protocol described in I/O FSM (Input/Output Finite State Machine). This enables the generation of more complete and consistent test sequence for conformance testing. The above functions are implemented by C++ language and included within RSPVTE (Railway Signaling Protocol Verification and Testing Environment).

• Annual Conference of KIPS
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• 2022.11a
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• pp.475-477
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• 2022

최근 강화 학습을 적용한 게임 AI 에 대한 연구가 활발히 진행되고 있다. 하지만 대부분 상용게임은 유한 상태 머신(Finite State Machine, FSM)을 이용한 스크립트 기반 AI 를 사용하기 때문에 복잡한 환경의 게임에서 불안정한 상태로 인해 적절한 강화 학습의 수행이 어렵다. 따라서 본 논문에서는 상용 게임 강화 학습 적용을 위하여 상태 정규화 및 Dense 보상 기반 강화 학습 기법을 제안한다. 제안한 기법을 상용 농구 게임에 적용하고 학습된 모델의 성능을 기존 FSM 기반 AI 와 비교를 통해 성능이 약 80% 증가한 결과를 확인하였다.

• Journal of KIISE:Software and Applications
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• v.28 no.9
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• pp.634-648
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• 2001

Message Sequence Charts(MSC) has been used to describe the interactions of numerous concurrent tasks in telecommunication software. After the MSC specification is verified in requirement analysis phase, it can be used not only to synthesize state-based design models, but also to generate test sequences. Until now, the verification is accomplished by generating global state transition graph using the location information only. In this paper, we extend the condition statement of MSC to describe the activation condition of scenarios and the change of state variables, and propose an approach to construct global finite state machine (GFSM) using this information. The GFSM only includes feasible states and transitions of the system. We can generate the test sequences using the existing FSM-based test sequence generation technology.

• Journal of Korea Multimedia Society
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• v.1 no.1
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• pp.109-119
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• 1998

This paper describes a research result on automatic generation of Abstract Test Suite from INAP protocol in formal specifications by applying many existing related algorithms such as Rural Chinese Postman Tour and UIO sequence concepts. We use the I/O FSM generated from SDL specifications and a characterizing sequence concepts. We use the I/O FSM generated from SDL specifications and a characterizing sequence, called UIO sequence, is defined for the I/O FSM. The UIO sequence is combined with the concept of Rural Chinese Postman tour to obtain an optimal test sequence. It also proposes an estimation methodology of the fault courage for the Test Suite obtained by our method and their translation into the standardized test notation TTCN.

• The Transactions of the Korea Information Processing Society
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• v.1 no.3
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• pp.391-397
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• 1994

In this paper, we have developed a PLD Designer which is a design tool for digital circuits design using PLD device. PLD designer consists of a state graphic editor to extract boolean equations from state table within 20 states of FSM and a pin map editor to assign pin map for PLD device(PAL16R4, PAL22V10, GAL16V8, etc), which is suitable for extracted boolean equations. Also pin map editor generates a necessary JEDEC file to implement PLD device by using fuse map and checksum algorithm. To verify extracted boolean equation, we have developed simulation test vector generation algorithm. The results of JEDEC files generated by PLD designer is same with the results of JEDEC files generated by PALASM.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.410-413
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• 2000

This paper suggests a methodology in which control signals for high-level synthesis are generated from SDL specification. SDL is based on EFSM(Extended Finite State Machine) model. Data path and control part are partitioned into representing data operations in the from of scheduled data flow graph and process behavior of an SDL code in forms of an abstract FSM. Resource allocation is performed based on the suggested architecture model and local control signals to drive allocated functional blocks are incorporated into an abstract FSM extracted from an SDL process specification. Data path and global controller acquired through suggested methodology are combined into structural VHDL representation and correctness of behavior for final circuit is verified through waveform simulation.