• Title/Summary/Keyword: Finite field arithmetic

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Faster MapToPoint over $F_{3^m}$ for Pairing-based Cryptosystems (페어링 암호 시스템을 위한 $F_{3^m}$에서의 효율적인 MapToPoint 방법)

  • Park, Young-Ho;Cho, Young-In;Chang, Nam-Su
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.21 no.6
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    • pp.3-12
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    • 2011
  • A hashing function that maps arbitrary messages directly onto curve points (MapToPoint) has non-negligible complexity in pairing-based cryptosystems. Unlike elliptic curve cryptosystems, pairing-based cryptosystems require the hashing function in ternary fields. Barreto et al. observed that it is more advantageous to hash the message to an ordinate instead of an abscissa. So, they significantly improved the hashing function by using a matrix with coefficients of the abscissa. In this paper, we improve the method of Barreto et al. by reducing the matrix. Our method requires only 44% memory of the previous result. Moreover we can hash a message onto a curve point 2~3 times faster than Barreto's Method.

Efficiently Hybrid $MSK_k$ Method for Multiplication in $GF(2^n)$ ($GF(2^n)$ 곱셈을 위한 효율적인 $MSK_k$ 혼합 방법)

  • Ji, Sung-Yeon;Chang, Nam-Su;Kim, Chang-Han;Lim, Jong-In
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.9
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    • pp.1-9
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    • 2007
  • For an efficient implementation of cryptosystems based on arithmetic in a finite field $GF(2^n)$, their hardware implementation is an important research topic. To construct a multiplier with low area complexity, the divide-and-conquer technique such as the original Karatsuba-Ofman method and multi-segment Karatsuba methods is a useful method. Leone proposed an efficient parallel multiplier with low area complexity, and Ernst at al. proposed a multiplier of a multi-segment Karatsuba method. In [1], the authors proposed new $MSK_5$ and $MSK_7$ methods with low area complexity to improve Ernst's method. In [3], the authors proposed a method which combines $MSK_2$ and $MSK_3$. In this paper we propose an efficient multiplication method by combining $MSK_2,\;MSK_3\;and\;MSK_5$ together. The proposed method reduces $116{\cdot}3^l$ gates and $2T_X$ time delay compared with Gather's method at the degree $25{\cdot}2^l-2^l with l>0.

Design of an Efficient Bit-Parallel Multiplier using Trinomials (삼항 다항식을 이용한 효율적인 비트-병렬 구조의 곱셈기)

  • 정석원;이선옥;김창한
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.13 no.5
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    • pp.179-187
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    • 2003
  • Recently efficient implementation of finite field operation has received a lot of attention. Among the GF($2^m$) arithmetic operations, multiplication process is the most basic and a critical operation that determines speed-up hardware. We propose a hardware architecture using Mastrovito method to reduce processing time. Existing Mastrovito multipliers using the special generating trinomial p($\chi$)=$x^m$+$x^n$+1 require $m^2$-1 XOR gates and $m^2$ AND gates. The proposed multiplier needs $m^2$ AND gates and $m^2$+($n^2$-3n)/2 XOR gates that depend on the intermediate term xn. Time complexity of existing multipliers is $T_A$+( (m-2)/(m-n) +1+ log$_2$(m) ) $T_X$ and that of proposed method is $T_X$+(1+ log$_2$(m-1)+ n/2 ) )$T_X$. The proposed architecture is efficient for the extension degree m suggested as standards: SEC2, ANSI X9.63. In average, XOR space complexity is increased to 1.18% but time complexity is reduced 9.036%.