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Pipelining of orthogonal Double-Rotation Digital Lattice Filters for High-Speed and Low-Power Implementation (고속 및 저파워 실현을 위한 직교 이중 회전 디지털 격자 필터의 파이프라인화)

  • 정진균;엄경배
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.12
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    • pp.2409-2417
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    • 1994
  • The ODR(orthogonal double-rotation) digital lattice filters have desirable properties for VLSI implementation such as local connection, regularity and pipelinability. These filters are also known to exhibit good numerical behavior for finite precision implementation. Although these filters can be pipelined by the cut-set localization procedure, it should be noted that the maximum sample rate obtained by this technique is limited by the feedback computations. In this paper, a pipelining method for the ODR digital lattice filter is proposed, by which the sample rate can be increased at any desired level. it is also shown that the low-power CMOS digital implementation of ODR digital lattice filters can be done successfully using our pipelining method. The pipelining method is based on the properties of the Schur algoithm, constrained filter design methods, and the polyphase decomposition technique.

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A new multi-stage SPSO algorithm for vibration-based structural damage detection

  • Sanjideh, Bahador Adel;Hamzehkolaei, Azadeh Ghadimi;Hosseinzadeh, Ali Zare;Amiri, Gholamreza Ghodrati
    • Structural Engineering and Mechanics
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    • v.84 no.4
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    • pp.489-502
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    • 2022
  • This paper is aimed at developing an optimization-based Finite Element model updating approach for structural damage identification and quantification. A modal flexibility-based error function is introduced, which uses modal assurance criterion to formulate the updating problem as an optimization problem. Because of the inexplicit input/output relationship between the candidate solutions and the error function's output, a robust and efficient optimization algorithm should be employed to evaluate the solution domain and find the global extremum with high speed and accuracy. This paper proposes a new multi-stage Selective Particle Swarm Optimization (SPSO) algorithm to solve the optimization problem. The proposed multi-stage strategy not only fixes the premature convergence of the original Particle Swarm Optimization (PSO) algorithm, but also increases the speed of the search stage and reduces the corresponding computational costs, without changing or adding extra terms to the algorithm's formulation. Solving the introduced objective function with the proposed multi-stage SPSO leads to a smart feedback-wise and self-adjusting damage detection method, which can effectively assess the health of the structural systems. The performance and precision of the proposed method are verified and benchmarked against the original PSO and some of its most popular variants, including SPSO, DPSO, APSO, and MSPSO. For this purpose, two numerical examples of complex civil engineering structures under different damage patterns are studied. Comparative studies are also carried out to evaluate the performance of the proposed method in the presence of measurement errors. Moreover, the robustness and accuracy of the method are validated by assessing the health of a six-story shear-type building structure tested on a shake table. The obtained results introduced the proposed method as an effective and robust damage detection method even if the first few vibration modes are utilized to form the objective function.

The cancellation performance of loop-back signal in wireless USN multihop relay node (무선 USN 멀티홉 중계 노드에서 루프백 신호의 제거 성능)

  • Lim, Seung-Gag;Kang, Dae-Soo
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.9 no.4
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    • pp.17-24
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    • 2009
  • This paper deals with the cancellation performance of loop back interference signal in the case of multihop relay of 16-QAM received signal at the USN radio network. For this, it is necessary to the exchange of information with long distance located station by means of the relay function between the node in the USN environment. In the relay node, the loop-back interference signal which the retransmitting signal is feedback to the receiver side due to the antenna of transmitter and receiver are co-used or very colsely located or using the nonlinear device. Due to this signal, the performance of USN system are degraded which are using the limited resource of frequency and power. For improve this, it is necessary to applying the adaptive signal processing algorithm in order to cancellating the unwanted loop-back interference signal at the frontend of receiver in relaying node, we can get the better system and multi hop performance. In the adaptive signal processing, we considered the 16-QAM signal which has a good spectral efficiency, firstly, than, the QR-Array RLS algorithm was used that has a fairly good convergence property and the solving the finite length problem in the H/W implementation. Finaly, we confirmed that the good elimination performanc was confirmed by computer simulation in the learing cuved and received signal constellation compared to the conventional RLS.

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Structural analysis of an 38 feet diffusion style for high-speed catamaran yacht (38피트급 보급형 고속 카타마란 요트의 구조해석)

  • Park, Joo-Shin;Ko, Jae-Yong;Lee, Kyoung-Woo;Oh, Woo-Jun
    • Journal of Navigation and Port Research
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    • v.33 no.3
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    • pp.167-174
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    • 2009
  • Recently, design technology of has been required such as catamaran yacht with high-speed according to expand a marine leisure industry. The domestic technical development for design and production of yacht is not actively than Canada, USA, Japan etc. However, with further development of yacht design & technology, it is need to develop a key technology related to increase the value of catamaran yacht. In the present paper, new guideline is suggest for catamaran yacht as like kinds of marine leisure ship in order for fundamental structure design and structural analysis for twin-hulled ship yacht and techniques for structural analysis as sea leisure ship in this research. The class of society has not been proposed formally about regulation and methodology for estimation of strength of small hight-speed craft with satisfying two conditions as noted; length less than 50meters, ratio of length to breadth less than 12. In the present study, we were adopted DNV (Yachts, Design Principles, Design Loads, Hull Structural Design) Rule and KR (FRP rule application guide) for scantling of structural members. Furthermore, ABS rule is used for structural calculation about application of loading conditions for catamaran yacht. This study can be available feedback role to manufacture of 38ft diffusion style for catamaran yacht. It is expected that this study will be a good reference in order to design of catamaran yacht with high-speed.

Comparative analysis of the digital circuit designing ability of ChatGPT (ChatGPT을 활용한 디지털회로 설계 능력에 대한 비교 분석)

  • Kihun Nam
    • The Journal of the Convergence on Culture Technology
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    • v.9 no.6
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    • pp.967-971
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    • 2023
  • Recently, a variety of AI-based platform services are available, and one of them is ChatGPT that processes a large quantity of data in the natural language and generates an answer after self-learning. ChatGPT can perform various tasks including software programming in the IT sector. Particularly, it may help generate a simple program and correct errors using C Language, which is a major programming language. Accordingly, it is expected that ChatGPT is capable of effectively using Verilog HDL, which is a hardware language created in C Language. Verilog HDL synthesis, however, is to generate imperative sentences in a logical circuit form and thus it needs to be verified whether the products are executed properly. In this paper, we aim to select small-scale logical circuits for ease of experimentation and to verify the results of circuits generated by ChatGPT and human-designed circuits. As to experimental environments, Xilinx ISE 14.7 was used for module modeling, and the xc3s1000 FPGA chip was used for module embodiment. Comparative analysis was performed on the use area and processing time of FPGA to compare the performance of ChatGPT products and Verilog HDL products.