• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.2
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• pp.93-99
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• 2011

In this paper, an ATSC(Advanced Television Standard Committee)-M/H(Mobile/Handheld) multiplexer is designed and implemented using an embedded Linux based hardware platform. The ATSC-M/H multiplexer is composed of a CPU(Central Processor Unit), an FPGA(Field-Programmable Gate Array), ASI(Asynchronous Serial Interface)/SMPTE310(Society of Motion Picture and Television Engineers310) interface board, and a GPS(Global Position System) clock processing block. The main functions of the ATSC-M/H multiplexer executed in the CPU and FPGA are described. The operation of the ATSC-M/H multiplexer is verified by processing its broadcast signal on a commercial receiver analyzer.

• Journal of Power Electronics
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• v.19 no.5
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• pp.1171-1181
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• 2019

Modular Multilevel Converter (MMC)-based HVDC power transmission using a real-time simulator is one of the key technologies in power electronics research. This paper introduces the design methodology of a physical MMC-HVDC control system based on a Field-Programmable Gate Array (FPGA), which has the advantage of high-speed parallel operation, and validates the accuracy of MMC-HVDC control when operated with a Real-Time Digital Simulator (RTDS). Finally, this paper compares and analyzes the characteristics of capacitor voltage balancing methods such as Nearest Level Control (NLC), NLC with a reduced switching frequency, and tolerance band modulation implemented on physical control system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.649-651
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• 2016

본 연구에서는 디지털 신호에 포함되어 있는 잡음을 효과적으로 제거하기 위한 방법으로 프로그램 가능한 디지털 FIR 필터를 제안한다. 이러한 필터는 Altera의 FPGA(Field Programmable Gate Array)인 cyclone II EP2C70F89618를 이용하여 설계하고 구현하였다. 데이터 신호 잡음 제거 알고리즘을 바탕으로 한 영상 신호 제거 결과는 출력 영상으로부터 알 수 있듯이 필터 적용 후 출력 영상은 적용 전의 출력 영상에 비해 월등히 구분이 가능한 출력 영상 특성을 보임을 확인하였다.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.414-415
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• 2019

본 논문은 HVDC(High Voltage Direct Current)에 적용된 MMC(Modular Multilevel Converter)의 제어 알고리즘 개발을 위한 HILS(Hardware In the Loop Simulation)을 위한 모델링 및 HILS 시스템 구축 예를 보인다. 전력 계통, MMC, 풍력 발전 등의 HILS 적용 MATLAB/SIMULINK 모델 및 FPGA(Field Programmable Gate Array)를 이용한 제어기 개발 내용을 보인다. 시뮬레이션 모델과 FPGA 제어기를 이용하여 구축한 OPAL-RT 기반의 실험 결과를 보인다.

• Journal of Sensor Science and Technology
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• v.31 no.1
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• pp.16-23
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• 2022

Cardiac disease is the most common cause of death worldwide. Therefore, detection and classification of electrocardiogram (ECG) signals are crucial to extend life expectancy. In this study, we aimed to implement an artificial intelligence signal recognition system in field programmable gate array (FPGA), which can recognize patterns of bio-signals such as ECG in edge devices that require batteries. Despite the increment in classification accuracy, deep learning models require exorbitant computational resources and power, which makes the mapping of deep neural networks slow and implementation on wearable devices challenging. To overcome these limitations, spiking neural networks (SNNs) have been applied. SNNs are biologically inspired, event-driven neural networks that compute and transfer information using discrete spikes, which require fewer operations and less complex hardware resources. Thus, they are more energy-efficient compared to other artificial neural networks algorithms.

• Proceedings of the Korea Information Processing Society Conference
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• 2024.05a
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• pp.47-50
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• 2024

희소 행렬은 대부분의 요소가 0 인 행렬이다. 이러한 희소 행렬-행렬 곱셈을 수행할 경우 0 인 데이터 또한 곱셈을 수행하니 불필요한 연산이 발생한다. 이러한 문제를 해결하고자 행렬 압축 알고리즘 또는 곱셈의 부분합의 수를 줄이는 연구들이 활발히 진행 중이다. 하지만 현재의 연구들은 주로 단일 행렬 연산에 집중되어 있어 FPGA(Field Programmable Gate Array)와 특정 용도로 사용하는 가속기에서는 리소스를 충분히 활용하지 못해 비효율적이다. 본 연구는 FPGA 의 모든 리소스를 사용하여 다중 희소 행렬 곱셈을 수행하는 아키텍처를 제안한다.

• Journal of Institute of Control, Robotics and Systems
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• v.22 no.8
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• pp.671-677
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• 2016

A Controller Area Network (CAN) is a serial communication protocol that is highly reliable and efficient in many aspects, such as wiring cost and space, system flexibility, and network maintenance. Therefore, it is chosen for the communication protocol between a single chip controller based on Field Programmable Gate Array (FPGA) and peripheral devices. In this paper, the design and implementation of CAN IP, which is written in VHSIC Hardware Description Language (VHDL), is presented. The implemented CAN IP is based on the CAN 2.0A specification. The CAN IP consists of three processes: clock generator, bit timing, and bit streaming. The clock generator process generates a time quantum clock. The bit timing process does synchronization, receives bits from the Rx port, and transmits bits to the Tx port. The bit streaming process generates a bit stream, which is made from a message received from a micro controller subsystem, receives a bit stream from the bit timing process, and handles errors depending on the state of the CAN node and CAN message fields. The implemented CAN IP is synthesized and downloaded into SmartFusion FPGA. Simulations using ModelSim and chip test results show that the implemented CAN IP conforms to the CAN 2.0A specification.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.5
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• pp.1089-1094
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• 2013

In this study, we propose how th implement a MDDI(Mobile Display Digital Interface) protocol packet generation method in software. MDDI protocol is widely used in mobile display device. MDDI protocol packets are generated by software within micro processor. This method needs the minimum hardware configuration. In order to implementation of this method, we design a hardware platform with a high performance microprocessor and a FPGA. The packets generated by software within microprocessor are converted into LVDS signals, and transmitted by hardware within FPGA. This study suggests the benefits of the way how software can easily create a variety of packet. But, this proposed method takes more time in packet transmission compared to the traditional method. This weakness remains as a future challenge, which can be soon improved.

• Journal of the Korean Society of Systems Engineering
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• v.14 no.2
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• pp.41-48
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• 2018

This paper describes the systems engineering development process for the Departure from Nucleate Boiling Ratio (DNBR) algorithm using FPGA. Current Core Protection Calculator System (CPCS) requirement and DNBR logic are analyzed in the reverse engineering phase and the new FPGA based DNBR algorithm is designed in the re-engineering phase. FPGA based DNBR algorithm is developed by VHSIC Hardware Description Language (VHDL) in the implementation phase and VHDL DNBR software is verified in the software Verification & Validation phase. Test cases are developed to perform the software module test for VHDL software modules. The APR 1400 simulator is used to collect the inputs data in 100%, 75%, and 50% reactor power condition. Test input signals are injected to the software modules following test case tables and output signals are compared with the expected test value. Minimum DNBR value from developed DNBR algorithm is validated by KEPCO E&C CPCS development facility. This paper summarizes the process to develop the FPGA-based DNBR calculation algorithm using systems engineering approach.

• Journal of Information Processing Systems
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• v.17 no.6
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• pp.1097-1114
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• 2021

The primary objective of this work was to discover a solution for the survival of people in an emergency flood. The geographical information was obtained from remote sensing techniques. Through helpline numbers, people who are in need request support. Although, it cannot be ensured that all the people will acquire the facility. A proper link is required to communicate with people who are at risk in affected areas. Mobile sensor networks with field-programmable gate array (FPGA) self-configurable radios were deployed in damaged areas for communication. Ad-hoc networks do not have a centralized structure. All the mobile nodes deploy a temporary structure and they act as a base station. The mobile nodes are involved in searching the spectrum for channel utilization for better communication. FPGA-based techniques ensure seamless communication for the survivors. Timely help will increase the survival rate. The received signal strength is a vital factor for communication. Cognitive radio ensures channel utilization in an effective manner which results in better signal strength reception. Frequency band selection was carried out with the help of the GRA-MADM method. In this study, an analysis of signal strength for different mobile sensor nodes was performed. FPGA-based implementation showed enhanced outcomes compared to software-based algorithms.