• 전자공학회논문지D
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• 제36D권5호
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• pp.36-43
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• 1999

새로운 방식의 직접 디지털 주파수 합성기(Direct Digital Frequency Synthesizer, DDFS)의 설계방식을 제시하였다. 배열형 CORDIC(Coordinate Rotate Digital Computer)을 해석함에 있어서 오차의 크기를 계산하였다. 오차에는 계산회수의 부족에서 발생하는 ‘반복회수오차’와 제한된 데이터 비트수를 사용함으로써 계산에 사용하지 못하는 유효숫자 이하를 버림으로써 발생하는‘절단오차’로 분류할 수 있다. 실제로 각 비트별로 오차를 측정해 보면 8비트시 7단, 16비트시 12단, 24비트시 20단으로 근최적화된 파이프라인 단수를 얻을 수 있었다. 이 DDFS는 FPGA칩으로 구현되었고, 측정결과 235MHz의 구동 클럭에서 안정된 동작을 보였으며, 11.75MHz의 최대 출력 주파수를 발생시켰다. 위상별 진폭값을 ROM에 저장하는 기존의 방식에 비하여, 보다 높은 정밀도와 처리속도를 보이며, 제조공정 역시 단순해 질 것이다. 특히 같은 비트를 채택한 경우 롬방식에 비하여 5배정도의 높은 정밀도를 얻었다.

• 정보보호학회논문지
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• 제28권5호
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• pp.1225-1231
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• 2018

FPGA(Field Programmable Gate Array)를 이용한 시스템 개발은 개발 시간 단축 및 비용 절감을 위해 제3자에게 아웃소싱하는 형태로 발전하고 있다. 이러한 과정에서 악의적인 기능 및 오작동을 유발하는 하드웨어 악성기능(Hardware Trojan)이 시스템에 유입될 위협 또한 증가하고 있다. 하드웨어 악성기능의 탐지를 위해 다양한 방법들이 제시되고 있으나 FPGA에 탑재되는 비트스트림을 직접 수정하는 형태의 하드웨어 악성기능은 기존에 제시된 방법으로 탐지하기 어렵다. 이러한 유형의 하드웨어 악성기능 탐지를 위해서는 비트스트림으로부터 구현된 회로를 식별 가능한 수준으로 역공학하는 과정이 필요하며, 회로를 구성하는 여러 요소 중 특히 신호의 입출력 흐름을 파악할 수 있는 연결 정보를 역공학하는 것이 중요하다. 본 논문에서는 FPGA 비트스트림으로부터 연결 정보를 복구하는 도구인 BIL을 분석하고 이를 개선하기 위한 방법을 제시한다.

• 대한전자공학회논문지SD
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• 제46권2호
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• pp.24-30
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• 2009

본 논문에서는 3GPP(Third Generation Partnership Project) Release 7 eHSPA(High Speed Packet Access for Evolution) UE(User Equipment) FDD(Frequency Division Duplex) 규격을 만족하는 단말 모뎀의 FPGA(Field Programmable Gate Array) 플랫폼 설계 및 이를 기반으로 한 효율적인 검증 방법에 대해 제안한다. 구현된 FPGA 모뎀 플랫폼은 물리 계층 지원을 위한 모뎀 보드, MCU(Micro Controller Unit)와 DSP(Digital Signal Processor) 코어로 구성되어 모뎀 보드를 제어를 위한 제어 보드, 그리고 RF(Radio Frequency) 및 기타 장비 접속을 위한 주변장치(Peripheral) 보드 등으로 구성된다. 그리고 검증 단계는 하드웨어-소프트웨어 연동 상관 정도에 따라 단순 기능 검증, 시나리오 검증 그리고 호 처리 및 시스템 성능 검증 등으로 규정화하여 진행되었고, 실제 구현적인 측면으로 저 전력 SoC(System On a Chip)를 위한 에뮬레이션 검증 기법도 제안한다.

• Nuclear Engineering and Technology
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• 제54권7호
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• pp.2444-2452
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• 2022

The field-programmable gate array (FPGA) is gaining popularity in industrial automation such as nuclear power plant instrumentation and control (I&C) systems due to the benefits of having non-existence of operating system, minimum software errors, and minimum common reason failures. Separate functions can be processed individually and in parallel on the same integrated circuit using FPGAs in comparison to the conventional microprocessor-based systems used in any plant operations. The use of FPGAs offers the potential to minimize complexity and the accompanying difficulty of securing regulatory approval, as well as provide superior protection against obsolescence. Wireless sensor networks (WSNs) are a new technology for acquiring and processing plant data wirelessly in which sensor nodes are configured for real-time signal processing, data acquisition, and monitoring. ZigBee (IEEE 802.15.4) is an open worldwide standard for minimum power, low-cost machine-to-machine (M2M), and internet of things (IoT) enabled wireless network communication. It is always a challenge to follow the specific topology when different Zigbee nodes are placed in a large network such as a plant. The research article focuses on the hardware chip design of different topological structures supported by ZigBee that can be used for monitoring and controlling the different operations of the plant and evaluates the performance in Vitex-5 FPGA hardware. The research work presents a strategy for configuring FPGA with ZigBee sensor nodes when communicating in a large area such as an industrial plant for real-time monitoring.

• 전기전자학회논문지
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• 제27권4호
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• pp.624-629
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• 2023

본 논문에서는 ESPRIT(estimation of signal parameters via rotational invariance techniques)알고리듬 기반 재구성 가능한 각도 추정기를 제안 및 설계하였다. ESPRIT은 배열 안테나(uniform linear array)의 천이불변(shift invariance) 성질을 이용해 배열 안테나에 도래하는 신호의 도래각을 추정하는 알고리듬이다. 하지만 여전히 ESPRIT 알고리즘은 공분산 행렬, 고윳값 분해 등 높은 복잡도를 가지는 연산을 필요로 하므로 실시간 도래각 추정을 위해 하드웨어 프로세서로 구현이 필요하다. ESPRIT에서 성능은 안테나 개수와 관련이 있으며, 응용에 따라 요구되는 안테나 수는 상이할 수 있다. 이에 본 논문에서는 응용되는 분야에 따라 성능을 높이고 연산 복잡도 문제를 시킬 수 있도록 2 ~ 8개의 가변 안테나 개수를 지원하는 ESPRIT 프로세서를 제안하였다. 또한, 제안된 ESPRIT 프로세서는 MI-ESPRIT 구조를 기반으로 배열 안테나의 다중 불변성을 활용하여 성능을 향상시켰으며, 최소자승법 알고리즘을 간소화 시켜 복잡도를 감소시켰다.

• Journal of Power Electronics
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• 제17권1호
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• pp.56-66
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• 2017

Fast and accurate fault detection is the primary step and one of the most important tasks in fault tolerant converters. In this paper, a fast and simple method is proposed to detect and diagnosis the faulty cell in a cascaded H-bridge multilevel inverter under a short circuit fault. In this method, the reference voltage is calculated using switching control pulses and DC-Link voltages. The comparison result of the output voltage and the reference voltage is used in conjunction with active cell pulses to detect the faulty cell. To achieve this goal, the cell which is active when the Fault signal turns to "0" is detected as the faulty cell. Furthermore, consideration of generating the active cell pulses is completely described. Since the main advantage of this method is its simplicity, it can be easily implemented in a programmable digital device. Experimental results obtained with an 11-level inverter prototype confirm the effectiveness of the proposed fault detection technique. In addition, they show that the diagnosis method is unaffected by variations of the modulation index.

• 정보저장시스템학회논문집
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• 제1권2호
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• pp.155-160
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• 2005

In this paper, the channel decoder promising reliable data retrieving in noisy holographic channel has been developed for holographic WORM(write once read many) system. It covers various DSP(digital signal processing) blocks, such as align mark detector, adaptive channel equalizer, modulation decoder and ECC(error correction code) decoder. The specific schemes of DSP are designed to reduce the effect of noises in holographic WORM(H-WORM) system, particularly in prototype of DAEWOO electronics(DEPROTO). For real time data retrieving, the channel decoder is redesigned for FPGA(field programmable gate array) based hardware, where DSP blocks calculate in parallel sense with memory buffers between blocks and controllers for driving peripherals of FPGA. As an input source of the experiments, MPEG2 TS(transport stream) data was used and recorded to DEPROTO system. During retrieving, the CCD(charge coupled device), capturing device of DEPROTO, detects retrieved images and transmits signals of them to the FPGA of hardware channel decoder. Finally, the output data stream of the channel decoder was transferred to the MPEG decoding board for monitoring video signals. The experimental results showed the error corrected BER(bit error rate) of less than $10^{-9}$, from the raw BER of DEPROTO, about $10^{-3}$. With the developed hardware channel decoder, the real-time video demonstration was possible during the experiments. The operating clock of the FPGA was 60 MHz, of which speed was capable of decoding up to 120 mega channel bits per sec.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제13권10호
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• pp.4865-4885
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• 2019

We propose a FPGA based design that performs real-time power-efficient analysis of heterogeneous sensor data using adaptive ANN on edge gateway of smart military wearables. In this work, four independent ANN classifiers are developed with optimum topologies. Out of which human activity, BP and toxic gas classifier are multiclass and ECG classifier is binary. These classifiers are later integrated into a single adaptive ANN hardware with a select line(s) that switches the hardware architecture as per the sensor type. Five versions of adaptive ANN with different precisions have been synthesized into IP cores. These IP cores are implemented and tested on Xilinx Artix-7 FPGA using Microblaze test system and LabVIEW based sensor simulators. The hardware analysis shows that the adaptive ANN even with 8-bit precision is the most efficient IP core in terms of hardware resource utilization and power consumption without compromising much on classification accuracy. This IP core requires only 31 microseconds for classification by consuming only 12 milliwatts of power. The proposed adaptive ANN design saves 61% to 97% of different FPGA resources and 44% of power as compared with the independent implementations. In addition, 96.87% to 98.75% of data throughput reduction is achieved by this edge gateway.

• 시스템엔지니어링학술지
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• 제14권2호
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• pp.73-82
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• 2018

In this work, a hardware based cryptographic module for the cyber security of nuclear power plant is developed using a system engineering approach. Nuclear power plants are isolated from the Internet, but as shown in the case of Iran, Man-in-the-middle attacks (MITM) could be a threat to the safety of the nuclear facilities. This FPGA-based module does not have an operating system and it provides protection as a firewall and mitigates the cyber threats. The encryption equipment consists of an encryption module, a decryption module, and interfaces for communication between modules and systems. The Advanced Encryption Standard (AES)-128, which is formally approved as top level by U.S. National Security Agency for cryptographic algorithms, is adopted. The development of the cyber security module is implemented in two main phases: reverse engineering and re-engineering. In the reverse engineering phase, the cyber security plan and system requirements are analyzed, and the AES algorithm is decomposed into functional units. In the re-engineering phase, we model the logical architecture using Vitech CORE9 software and simulate it with the Enhanced Functional Flow Block Diagram (EFFBD), which confirms the performance improvements of the hardware-based cryptographic module as compared to software based cryptography. Following this, the Hardware description language (HDL) code is developed and tested to verify the integrity of the code. Then, the developed code is implemented on the FPGA and connected to the personal computer through Recommended Standard (RS)-232 communication to perform validation of the developed component. For the future work, the developed FPGA based encryption equipment will be verified and validated in its expected operating environment by connecting it to the Advanced power reactor (APR)-1400 simulator.

• Nuclear Engineering and Technology
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• 제55권8호
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• pp.2873-2878
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• 2023

The purpose of this study is to perform radiation monitoring by acquiring gamma images and real-time optical images for ^99mTc vial source using charge couple device (CCD) cameras equipped with the proposed compact gamma camera. The compact gamma camera measures 86×65×78.5 mm³ and weighs 934 g. It is equipped with a metal 3D printed diverging collimator manufactured in a 45 field of view (FOV) to detect the location of the source. The circuit's system uses system-on-chip (SoC) and field-programmable-gate-array (FPGA) to establish a good connection between hardware and software. In detection modules, the photodetector (multi-pixel photon counters) is tiled at 8×8 to expand the activation area and improve sensitivity. The gadolinium aluminium gallium garnet (GAGG) measuring 0.5×0.5×3.5 mm³ was arranged in 38×38 arrays. Intrinsic and extrinsic performance tests such as energy spectrum, uniformity, and system sensitivity for other radioisotopes, and sensitivity evaluation at edges within FOV were conducted. The compact gamma camera can be mounted on unmanned equipment such as drones and robots that require miniaturization and light weight, so a wide range of applications in various fields are possible.