• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.261-267
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• 2001

This paper presents the architecture of multiple-queue manager for input-queued switch, which has arbitration latency, and the design of the chip. The proposed architecture of multiple-queue manager provides wire-speed routing with a pipelined buffer management, and the tolerance of requests and grants data transmission latency between the input queue manager and central arbiter using a new request control method, which is based on a high-speed shifter. The multiple-input-queue manager has been implemented in a field programmable gate array chip, which provides OC-48c port speed. It enhances the maximum throughput of the input queuing switch up to 98.6% with 128-cell shared input buffer in 16$\times$16 switch size.

• 제어로봇시스템학회:학술대회논문집
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• 1999.10a
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• pp.9-12
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• 1999

This paper presents the development of a control architecture for the autonomous underwater vehicle (AUV) with VARIVEC (variable vector) propeller. Moreover this paper also describes the new technique of controlling the servomotors using the Field Programmable Gate Array (FPGA). The AUVs are being currently used fur various work assignments. For the daily measuring task, conventional AUV are too large and too heavy. A small AUV will be necessary for efficient exploration and investigation of a wide range of a sea. AUVs are in the phase of research and development at present and there are still many problems to be solved such as power resources and underwater data transmission. Further, another important task is to make them smaller and lighter for excellent maneuverability and low power. Our goal is to develop a compact and light AUV having the intelligent capabilities. We employed the VARIVEC propeller system utilizing the radio control helicopter elements, which are swash plate and DC servomotors. The VARIVEC propeller can generate six components including thrust, lateral force and moment by changing periodically the blade angle of the propeller during one revolution. It is possible to reduce the number of propellers, mechanism and hence power sources. Our control tests were carried out in an anechoic tank which suppress the reflecting effects of the wall surface. We tested the developed AUV with required performance. Experimental results indicate the effectiveness of our approach. Control of VARIVEC propeller was realized without any difficulty.

• Journal of Korea Multimedia Society
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• v.23 no.2
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• pp.317-327
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• 2020

R&D(Research and Development) efficiency analysis is a very important issue in academia and industry. Although many studies have been conducted to analyze R&D(Research and Development) efficiency since the past, studies that analyzed R&D(Research and Development) efficiency considering both patentability and patent quality efficiency according to the financial performance of a company do not seem to have been actively conducted. In this study, measuring the patent application and patent quality efficiency according to financial performance, patent quality efficiency according to patent application were applied to corporate groups related to artificial intelligence hardware technology defined as GPU(Graphics Processing Unit), FPGA(Field Programmable Gate Array), ASIC(Application Specific Integrated Circuit) and Neuromorphic. We analyze the efficiency empirically and use Data Envelopment Analysis as a measure of efficiency. This study examines which companies group has high R&D(Research and Development) efficiency about artificial intelligence hardware technology.

• Journal of Power Electronics
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• v.8 no.4
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• pp.363-370
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• 2008

In this paper, three kinds of PWM strategies for a three-phase current-fed dc/dc converter are proposed and compared in terms of losses and voltage transfer ratio. Each PWM strategy is described graphically and their switching losses are analyzed. With the proposed PWM C strategy, one turn-off switching of each bridge switch is eliminated to reduce switching losses under the same switching frequency. In addition, RMS current through the bridge switches is lowered by using parallel connection between two bridge switches and thus, conduction losses of the switches are reduced. Further, copper losses of the transformer are decreased due to the reduced RMS current of each transformer's winding. Therefore, total losses are minimized and the efficiency of the converter is improved by using the proposed PWM C strategy. Digital signal processor (DSP: TI320LF2407) and a field-programmable gate array (FPGA: EPM7128) board are used to generate PWM patterns for three-phase bridge and clamp MOSFETs. A 500W prototype converter is built and its experimental results verify the validity of the proposed PWM strategies.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2005.11a
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• pp.101-104
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• 2005

본 논문에서는 국내에서 채택한 ATSC-DTV (Advanced Television System Committee-Digital Television)의 단일주파 수망 (SFN; Single Frequency Network) 구성을 위한 TxID (Transmitter Identification)용 ZCD (Zero Correlation Duration)확산코드 기반의 부분상관 정합필터를 새롭게 제안하였다. 본 논문에서 제안한 정합필터의 구현 알고리즘은 TxID에 있어서 기존의 정합필터 구조를 적용할 경우에 발생되는 소비전력 문제나 하드웨어 구현의 어려움을 획기적으로 해결할 수 있다는 잇점을 갖는다. 따라서 본 논문에서는 이러한 다양한 잇점을 갖는 새롭게 제안한 ZCD용 부분상관 정합필터를 FPGA (Field Programmable Gate Array)를 이용한 디지털 하드웨어로 구현하고 그 성능을 분석함으로써 유용성을 확인하였다.

• Journal of electromagnetic engineering and science
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• v.11 no.4
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• pp.304-310
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• 2011

The application of time-domain methods in emission measurement instruments allows for a reduction in scan time by several orders of magnitude and for new evaluation methods to be realized such as the real-time spectrogram to characterize transient emissions. In this paper two novel systems for time-domain EMI measurements above 1 GHz are presented. The first system combines ultra-fast analog-to-digital-conversion and real-time digital signal processing on a field-programmable-gate-array (FPGA) with ultra-broadband multi-stage down-conversion to enable measurements in the range from 10 Hz to 26 GHz with high sensitivity and full-compliance with the requirements of CISPR 16-1-1. The required IF bandwidths were added to allow for measurements according to MIL-461F and DO-160F. The second system realizes a system of time-interleaved analog-to-digital converters (ADCs) and has an upper bandwidth limit of 4 GHz. With the implementation of an automatic mismatch calibration, the system fulfills CISPR 16-1-1 dynamic range requirements. Measurements of the radiated emissions of electronic consumer devices and household appliances like the non-stationary emissions of a microwave oven are presented. A measurement of a personal computer's conducted emissions on a power supply line according to DO-160F is given.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.264-267
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• 2002

This paper presents the design of a pipelined virtual output queue routing engine for an advanced input-queued ATM switch, which has a serial cross bar structure. The proposed routing engine has been designed for wire-speed routing with a pipelined buffer management. It provides the tolerance of requests and grants data transmission latency between the routing engine and central arbiter using a new request control method that is based on a high-speed shifter. The designed routing engine has been implemented in a field programmable gate array (FPGA) chip with a 77MHz operating frequency, 16$\times$16 switch size, and 2.5Gbps/port speed.

• ETRI Journal
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• v.37 no.4
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• pp.752-765
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• 2015

We propose a novel post-processing algorithm and its very-large-scale integration architecture that simultaneously uses the passive and active stereo vision information to improve the reliability of the three-dimensional disparity in a hybrid stereo vision system. The proposed architecture consists of four steps - left-right consistency checking, semi-2D hole filling, a tiny adaptive variance checking, and a 2D weighted median filter. The experimental results show that the error rate of the proposed algorithm (5.77%) is less than that of a raw disparity (10.12%) for a real-world camera image having a $1,280{\times}720$ resolution and maximum disparity of 256. Moreover, for the famous Middlebury stereo image sets, the proposed algorithm's error rate (8.30%) is also less than that of the raw disparity (13.7%). The proposed architecture is implemented on a single commercial field-programmable gate array using only 13.01% of slice resources, which achieves a rate of 60 fps for $1,280{\times}720$ stereo images with a disparity range of 256.

• Journal of Power Electronics
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• v.16 no.1
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• pp.190-204
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• 2016

An active front end (AFE) is required for a three-phase induction motor (IM) fed by a voltage source inverter (VSI), because of the increasing need to derive quality current from the utility end without sacrificing the power factor (PF). This study investigates a proportional-plus-integral (PI) controller based AFE topology that uses a super-lift converter (SLC). The significance of the proposed SLC, which converts rectified AC supply to geometrically proceed ripple-free DC supply, is explained. Variations in several power quality parameters in the intended IM drive for 0% and 100% loading conditions are demonstrated. A simulation is conducted by using MATLAB/Simulink software, and a prototype is built with a field programmable gate array (FPGA) Spartan-6 processor. Simulation results are correlated with the experimental results obtained from a 0.5 HP IM drive prototype with speed feedback and a voltage/frequency (V/f) control strategy. The proposed AFE topology using SLC is suitable for three-phase IM drives, considering the supply end PF, the DC-link voltage and current, the total harmonic distortion (THD) in supply current, and the speed response of IM.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.34 no.2
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• pp.101-105
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• 2006

The Engineering Model of STSAT-2 on-board computer(OBC) was developed and tested completely with other sub-systems. The on-board computer of STSAT-2 has a high- performance PowerPC processors and a structure of centralized network communication. In addition, a lot of logics are implemented by Field Programmable Gate Array, such as interrupt controller, watchdog timer and UART. It could make the weight and size of OBC lighter and smaller. Also, the STSAT-2 on-board computer has more improved tolerance against Single Event Upsets and faults than that of the STSAT-1.