• The Journal of Korean Institute of Communications and Information Sciences
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• v.11 no.1
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• pp.53-63
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• 1986

In this paper the decoder of nonbinary code satisfying R>1/t has been designed and constructed, where R is the code rate and t is the error correcting capability. In order to design the error trapping decoder, the concept of covering monomial is used and them the decoder system using the (15, 11) Reed-Solomon code is implemented. Without Galois Fiedl multiplication and division circuits, the decoder system is simply constructed. In the decoding process, it takes 60clocks to decode one code word. Two symbol errors and eight binary burst errors are simultaneously corrected. This coding system is shown to be efficient when the channel error probability is approximately from $5{\times}10^-4$~$5{\times}10^-5$.

• Education of Primary School Mathematics
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• v.10 no.2
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• pp.141-149
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• 2007

It is undeniably important to bring up a solution capability of arithmetic word problems in the elementary mathematical education. The goal of this study is to acquire the implication for remedial instruction on arithmetic word problems solving through surveying elementary school students' difficulties in the solving of arithmetic word problems. In order to do it, this study was intended to analyze the following two aspects. First, it was analyzed that they generally felt more difficulties in which field among addition, subtraction, multiplication and division word problems. Second, with the result of the first analysis, it was examined that they solved it by imagining as which sphere of the other word problems. Also, the cause of their error on the word problem solving was analyzed by the interview. From the foregoing analyses, the following implications for remedial instruction on arithmetic word problems solving are acquired. First, the accumulation of learning deficiency must be diminished through the remedial instruction. Second, it must help students to understand the given problem and to make of what the goal of problem is. Third, it must help students to form a good habit for reading the problem and to understand the context of problem. forth, the teacher must help students to review and reflect their problem-solving processes.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.254-256
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• 2019

소수체 GF(p)와 이진체 $GF(2^m)$ 상의 다중 타원곡선을 지원하는 듀얼 필드 ECC (DF-ECC) 프로세서를 설계하였다. DF-ECC 프로세서의 저면적 설와 다양한 타원곡선의 지원이 가능하도록 워드 기반 몽고메리 곱셈 알고리듬을 적용한 유한체 곱셈기를 저면적으로 설계하였으며, 페르마의 소정리(Fermat's little theorem)를 유한체 곱셈기에 적용하여 유한체 나눗셈을 구현하였다. 설계된 DF-ECC 프로세서는 스칼라 곱셈과 점 연산, 그리고 모듈러 연산 기능을 가져 다양한 공개키 암호 프로토콜에 응용이 가능하며, 유한체 및 모듈러 연산에 적용되는 파라미터를 내부 연산으로 생성하여 다양한 표준의 타원곡선을 지원하도록 하였다. 설계된 DF-ECC는 FPGA 구현을 하드웨어 동작을 검증하였으며, 0.18-um CMOS 셀 라이브러리로 합성한 결과 22,262 GEs (gate equivalences)와 11 kbit RAM으로 구현되었으며, 최대 100 MHz의 동작 주파수를 갖는다. 설계된 DF-ECC 프로세서의 연산성능은 B-163 Koblitz 타원곡선의 경우 스칼라 곱셈 연산에 885,044 클록 사이클이 소요되며, B-571 슈도랜덤 타원곡선의 스칼라 곱셈에는 25,040,625 사이클이 소요된다.

• Nuclear Engineering and Technology
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• v.53 no.11
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• pp.3665-3674
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• 2021

One of the important parts of the in-core fuel management is loading pattern optimization (LPO). The loading pattern optimization as a reasonable design of the in-core fuel management can improve both economic and safe aspects of the nuclear reactor. This work proposes the hybrid of fuzzy logic controller with harmony search algorithm (HS) for loading pattern optimization in a pressurized water reactor. The music improvisation process to find a pleasing harmony is inspiring the harmony search algorithm. In this work, the adjustment of the harmony search algorithm parameters such as the bandwidth and the pitch adjustment rate are increasing performance of the proposed algorithm which is done through a fuzzy logic controller. Hence, membership functions and fuzzy rules are designed to improve the performance of the HS algorithm and achieve optimal results. The objective of the method is finding an optimum core arrangement according to safety and economic aspects such as reduction of power peaking factor (PPF) and increase of effective multiplication factor (Keff). The proposed approach effectiveness has been tried in two cases, Michalewicz's bivariate function problem and NEACRP LWR core. The results show that by using fuzzy harmony search algorithm the value of the fitness function is improved by 15.35%. Finally, with regard to the new solutions proposed in this research it could be used as a trustworthy method for other optimization issues of engineering field.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.686-689
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• 2009

This paper describes a scalar multiplier for Elliptic curve cryptography. The scalar multiplier has 163-bits key size which supports the specifications of smart card standard. To reduce the computational complexity of scalar multiplication on finite field $GF(2^{163})$, the Non-Adjacent-Format (NAF) conversion algorithm based on complementary recoding is adopted. The scalar multiplier core synthesized with a $0.35-{\mu}m$ CMOS cell library has 32,768 gates and can operate up to 150-MHz@3.3-V. It can be used in hardware design of Elliptic curve cryptography processor for smart card security.

• International Journal of Computer Science & Network Security
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• v.22 no.9
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• pp.414-426
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• 2022

Elliptic Curve Cryptography (ECC) is one of the finest cryptographic technique of recent time due to its lower key length and satisfactory performance with different hardware structures. In this paper, a High Throughput Multiplier architecture is introduced for Elliptic Cryptographic applications based on concurrent computations. With the aid of the concurrent computing approach, the High Throughput Concurrent Computation (HTCC) technology that was just presented improves the processing speed as well as the overall efficiency of the point-multiplier architecture. Here, first and second distinct group operation of point multiplier are combined together and synthesised concurrently. The synthesis of proposed HTCC technique is performed in Xilinx Virtex - 5 and Xilinx Virtex - 7 of Field-programmable gate array (FPGA) family. In terms of slices, flip flops, time delay, maximum frequency, and efficiency, the advantages of the proposed HTCC point multiplier architecture are outlined, and a comparison of these advantages with those of existing state-of-the-art point multiplier approaches is provided over GF(2¹⁶³), GF(2²³³) and GF(2²⁸³). The efficiency using proposed HTCC technique is enhanced by 30.22% and 75.31% for Xilinx Virtex-5 and by 25.13% and 47.75% for Xilinx Virtex-7 in comparison according to the LC design as well as the LL design, in their respective fashions. The experimental results for Virtex - 5 and Virtex - 7 over GF(2²³³) and GF(2²⁸³)are also very satisfactory.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.84-95
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• 2006

In H/W implementation for the finite field the use of normal basis has several advantages, especially, the optimal normal basis is the most efficient to H/W implementation in $GF(2^m)$. In this paper, we propose a new, simpler, parallel multiplier over $GF(2^m)$ having a Gaussian normal basis of type k, which performs multiplication over $GF(2^m)$ in the extension field $GF(2^{mk})$ containing a type-I optimal normal basis. For k=2,4,6 the time and area complexity of the proposed multiplier is the same as tha of the best known Reyhani-Masoleh and Hasan multiplier.

• Korean Journal of Organic Agriculture
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• v.8 no.1
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• pp.89-99
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• 1999

To do mass multiplication of plug seedlings in potatoes, apical stem cuttings originated from virus-free microtubers were cut to one-two internodes and transplanted into the plug-tray. After 10days, we applied Chitosan and Wood Extraction on rooting and tuber formation of plug seedlings. To improve field adaptability of plug seedlings, rooted cuttings with a height of 20cm after 20days of cutting were transplanted ito the fields, We applied 500~2000ppm Chitosan on growth characteristics and tuber formation of that. The above and underground growths, such as plant height and number of leaves were significantly more vigorous after treatment with 500~1,000ppm Chitosan and 2,000ppm Wood Extraction, the spray treatment was carried out five times at intervals of four days after ten days of transplanting. T-N, K, P, Mg and Na, were higher as the concentrations of chitosan and Wood Extraction were higher. The growth and tuber yield in plug seedlings planting plot and seed potatoes planting plot were effectively highter as foliar application of Chitosan(500~2,000ppm) was done after planting the plot. T-N content in leaves and tuber was higher as the concentration of Chitosan was high. A similar tendency was shown in K, P and Mg. In the small tuber(under 30g), the number of tubers and tuber yield were relatively increased in the seed potatoes planting plot, but the large tubers(over 80g) yield was higher in the plug seedlings planting plot, and in order to increase tuber yield in plug seedlings it was necessary to add plant density to the field.

• The Journal of the Acoustical Society of Korea
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• v.34 no.3
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• pp.219-226
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• 2015

In this paper, derivation of the STL (Sound Transmission Loss) of a square plate installed in an impedance tube is discussed using an analytic method. Coupled motion of the plate vibration and acoustic field is considered. Vibration of the plate and pressure field inside the tube are expressed in terms of the infinite series of modal functions. Under the plane wave assumption, it is shown that consideration of the first few modes yields sufficiently accurate results. When the boundary of the plate is clamped, vibration mode is assumed as a multiplication of the beam modes corresponding to the crosswise directions. The natural frequencies of the clamped plate are calculated using the Rayleigh-Ritz method. It is found that the STL shows a dip at the lowest natural frequency of the plate, and increases as the frequency decreases below the natural frequency. Comparison of the result in this paper with the STL obtained by measurements and FE computations in the reference shows an excellent agreement.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.45-58
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• 2006

In H/W implementation for the finite field, the use of normal basis has several advantages, especially, the optimal normal basis is the most efficient to H/W implementation in $GF(2^m)$. In this paper, we propose a new, simpler, parallel multiplier over $GF(2^m)$ having a Gaussian normal basis of type k, which performs multiplication over $GF(2^m)$ in the extension field $GF(2^{mk})$ containing a type-I optimal normal basis. For k=2,4,6 the time and area complexity of the proposed multiplier is the same as tha of the best known Reyhani-Masoleh and Hasan multiplier