• Journal of KSNVE
• /
• v.9 no.1
• /
• pp.131-140
• /
• 1999

A method to reconstruct the sound field around a Korean bell is developed. The sound radiation problem is formulated based on the boundary element method by using the algorithm of the acoustical holography. Sound pressures at the hologram surface are measured and used as input data for the analysis program that was developed in this study. An error minimization scheme is presented to overcome difficulties that arise in the backward reconstruction of the BEM-based acoustical holography In the model fictitious source surfaces were also introduced to reduce the complexity stemmed from the source shape. The sound field associated with the (4.0) vibrational mode of the Korean bell was visualized and verified experimentally.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.59 no.10
• /
• pp.1917-1922
• /
• 2010

Near-Field Communication (NFC) is a short-range wireless communication technology evolved from RFID especially for the exchange of data between active and passive devices. This paper presents the mathematical models for the signal path of a NFC transceiver system and a behavioral simulation platform using MATLAB simulink. The approximated mathematical models simplify the simulation complexity of a transceiver and provide a quick evaluation. With this calculation platform, we can evaluate the system performance caused by the noise and the non-linearity of the individual blocks, and caused by system variables such as Effective Number of Bits (ENOB) of ADC and filter cutoff frequency. This platform provides us with a rapid prototyping, a reliable system design, and an efficient risk management during development of the NFC transceiver ICs.

• Communications of the Korean Mathematical Society
• /
• v.18 no.1
• /
• pp.159-168
• /
• 2003

In this paper we discuss the Construction Of 3 new extension field of characteristic odd and analyze the complexity of arithmetic operations over such a field. Also we show that it is suitable for Elliptic Curve Cryptosystems(ECC) and Digital Signature Algorithm(DSA, 〔7〕) as an underlying field. In particular, our digital signature scheme is at least twice as efficient as DSA.

• Proceedings of the IEEK Conference
• /
• 2002.07a
• /
• pp.30-33
• /
• 2002

To obtain good performance of radial basis function (RBF) neural networks, it needs very careful consideration in design. The selection of several parameters such as the number of centers and widths of the radial basis functions must be considered carefully since they critically affect the network's performance. We propose a learning algorithm for growing of complexity of RBF neural networks which is adapted automatically according to the complexity of tasks. The algorithm generates a new basis function based on the errors of network, the percentage of decreasing rate of errors and the nearest distance from input data to the center of hidden unit. The RBF's center is located at the point where the maximum of absolute interference error occurs in the input space. The width is calculated based on the standard deviation of distance between the center and inputs data. The steepest descent method is also applied for adjusting the weights, centers, and widths. To demonstrate the performance of the proposed algorithm, general problem of function estimation is evaluated. The results obtained from the simulation show that the proposed algorithm for RBF neural networks yields good performance in terms of convergence and accuracy compared with those obtained by conventional multilayer feedforward networks.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.25 no.5
• /
• pp.979-984
• /
• 2015

In this paper, we proposed a Semi-Systolic multiplier of $GF(2^n)$ with Type II optimal Normal Basis. Comparing the complexity of the proposed multiplier with Chiou's multiplier proposed in 2012, it is saved $2n^2+44n+26$ in total transistor numbers and decrease 4 clocks in time delay. This means that, for $GF(2^{333})$ of the field recommended by NIST for ECDSA, the space complexity is 6.4% less and the time complexity of the 2% decrease. In addition, this structure has an advantage as applied to Chiou's method of concurrent error detection and correction in multiplication of $GF(2^n)$.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.10 no.3
• /
• pp.193-202
• /
• 2010

This paper presents a high-speed low-complexity pipelined Reed-Solomon (RS) (255,239) decoder using pipelined reformulated inversionless Berlekamp-Massey (pRiBM) algorithm and its folded version (PF-RiBM). Also, this paper offers efficient pipelining and folding technique of the RS decoders. This architecture uses pipelined Galois-Field (GF) multipliers in the syndrome computation block, key equation solver (KES) block, Forney block, Chien search block and error correction block to enhance the clock frequency. A high-speed pipelined RS decoder based on the pRiBM algorithm and its folded version have been designed and implemented with 90-nm CMOS technology in a supply voltage of 1.1 V. The proposed RS(255,239) decoder operates at a clock frequency of 700 MHz using the pRiBM architecture and also operates at a clock frequency of 750 MHz using the PF-RiBM, respectively. The proposed architectures feature high clock frequency and low-complexity.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.9 no.6
• /
• pp.2201-2216
• /
• 2015

Peak to average power ratio (PAPR) is one of the main imperfections in the broadband communication systems with multiple carriers. In this paper, a new crest factor reduction (CFR) scheme based on interleaved phase sequence called Dummy Sequence Insertion Enhanced Partial Transmit Sequence (DSI-EPTS) is proposed which effectively reduces the PAPR while at the same time keeps the total complexity low. Moreover, the prototype of the proposed scheme in field programmable gate array (FPGA) is demonstrated. In DSI-EPTS scheme, a new matrix of phase sequence is defined which leads to a significant reduction in hardware complexity due to its less searching operation to extract the optimum phase sequence. The obtained results show comparable performance with slight difference due to the FPGA constraints. The results show 5 dB reduction in PAPR by applying the DSI-EPTS scheme with low complexity and low power consumption.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.1C
• /
• pp.140-148
• /
• 2008

Using the self duality of an optimal normal basis(ONB) of type II, we present a bit parallel and bit serial systolic arrays over GF($2^m$) which has a low hardware complexity and a low latency. We show that our multiplier has a latency m+1 and the basic cell of our circuit design needs 5 latches(flip-flops). Comparing with other arrays of the same kinds, we find that our array has significantly reduced latency and hardware complexity.

• Journal of The Korean Digital Architecture Interior Association
• /
• v.12 no.2
• /
• pp.15-23
• /
• 2012

Today, rapid changes in technologies and everyday lives due to the Internet make it is difficult to make predictions about the future. Generally, the best way to predict the future has been proposed by experts. Although expert opinions are very important, they are liable to produce incorrect results due to human error, insufficient information regarding future outcomes and a state of connectedness between people, among other reasons. One of the ways to reduce these mistakes is to provide objective information to the experts. There are many studies that focus on the collection of objective material from papers, patents, reports and the Internet, among other sources. This research paper seeks to develop a forecasting method using World Wide Web search results according to the Google search engine and a network analysis, which is generally used to analyze a social network analysis(SNA). In particular, this paper provides a method to analyze a complexity network and to discover important technologies in the construction field. This approach may make it possible to enhance the overall performance of forecasting method and help us understand the complex system.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.8 no.9
• /
• pp.3266-3285
• /
• 2014

With limited computing and storage resources, many network applications of encryption algorithms require low power devices and fast computing components. CHESS-64 is designed by employing simple key scheduling and Data-Dependent operations (DDO) as main cryptographic components. Hardware performance for Field Programmable Gate Arrays (FPGA) and for Application Specific Integrated Circuits (ASIC) proves that CHESS-64 is a very flexible and powerful new cipher. In this paper, the security of CHESS-64 block cipher under related-key differential cryptanalysis is studied. Based on the differential properties of DDOs, we construct two types of related-key differential characteristics with one-bit difference in the master key. To recover 74 bits key, two key recovery algorithms are proposed based on the two types of related-key differential characteristics, and the corresponding data complexity is about $2^{42.9}$ chosen-plaintexts, computing complexity is about $2^{42.9}$ CHESS-64 encryptions, storage complexity is about $2^{26.6}$ bits of storage resources. To break the cipher, an exhaustive attack is implemented to recover the rest 54 bits key. These works demonstrate an effective and general way to attack DDO-based ciphers.