• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.6
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• pp.1231-1243
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• 1997

Digital satellite communication channels have nonlinearities with memory due to saturation characteristics of traveling wave tube amplifier in the satellite and transmitter/receiver linear filters. In this paper, we propose a network structure and a learning algorithm for complex pi-sigma network (CPSK) and exploit CPSN in the problem of equalization of nonlinear satellite channels. The proposed CPSN is a complex-valued extension of real-valued pi-sigma network that is a higher-order feedforward network with fast learning while greatly reducing network complexity by utilizing efficient form of polynomials for many input variables. The performance of the proposed CPSN is demonstrated by computer simulations on the equalization of complex-valued QPSK input symbols distorted by a nonlinear channel modeled as a Volterra series and additive noise. The results indicate that the CPSN shows good equalization performance, fast convergence, and less computations as compared to conventional higher-order models such as Volterra filters.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.7
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• pp.1086-1093
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• 2001

A new linearization technique for RF high-power amplifiers(HPAs) using n-th order error signal generator (ESGn) is proposed. The n-th order ESG generates an error signal based on the complex envelope transfer characteristics of the HPA, which is combined at the output of the HPA. Therefore, the higher-order nonlinearlities are not affected by the ESG$\_$n/ and the stability of the linearized system is guaranteed due to the inherent open-loop configuration. Moreover, the output delay loss can be avoided, because the error signal is generated with the input signal of the HPA. The IMD(intermodulation distortion) improvement obtained applying the ESG$\_$7/ to 5 W class A HPA in cellular band demonstrates the feasibility of the proposed postdistortion system.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.39-46
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• 2016

This paper describes the third order feedforward delta-sigma modulator with inverter-based integrators and a 1.5bit comparator for the application of audio signal processing. The proposed 3rd-order delta-sigma modulator is multi-bit structure using 1.5 bit comparator instead of operational amplifier. This delta-sigma modulator has high SNR compared with single-bit 4th-order delta-sigma modulator in a low OSR. And it minimizes power consumes and simplified circuit structure using inverter-based integrator and using inverter-based integrator as analogue adder. The modulator was designed with 0.18um CMOS standard process and total chip area is $0.36mm^2$. The measured power cosumption is 28.8uW in a 0.8V analog supply and 66.6uW in a 1.8V digital supply. The measurement result shows that the peak SNDR of 80.7 dB, the ENOB of 13.1bit and the dynamic range of 86.1 dB with an input signal frequency of 2.5kHz, a sampling frequency of 2.56MHz and an oversampling rate of 64. The FOM (Walden) from the measurement result is 269 fJ/step, FOM (Schreier) was calculated as 169.3 dB.