• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.28-33
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• 2008

This paper presents a continuous-time equalizer adopting a clock loss tracking technique for digital display interface. This technique uses bottom hold circuit to detect the incoming clock loss. The generated loss signal is directly fed to equalizer filters, building adaptive feed-forward loops which contribute the stability of the system. The design was done in $0.18{\mu}m$ CMOS technology. Experimental results summarize that eye-width of minimum 0.7UI is achieved until -33dB channel loss at 1.65Gbps. The average power consumption of the equalizer is a maximum 10mW, a very low value in comparison to those of previous researches, and the effective area is $0.127mm^2$.

• Journal of Power Electronics
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• v.16 no.1
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• pp.297-309
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• 2016

Grid-connected inverters (GCIs) with an LCL output filter have the ability of attenuating high-frequency (HF) switching ripples. However, by using only grid-current control, the system is prone to resonances if it is not properly damped, and the current distortion is amplified significantly under highly distorted grid conditions. This paper proposes a synchronous reference frame equivalent proportional-integral (SRF-EPI) controller in the αβ stationary frame using the parallel virtual resistance-based active damping (PVR-AD) strategy for grid-interfaced distributed generation (DG) systems to suppress LCL resonance. Although both a proportional-resonant (PR) controller in the αβ stationary frame and a PI controller in the dq synchronous frame achieve zero steady-state error, the amplitude- and phase-frequency characteristics differ greatly from each other except for the reference tracking at the fundamental frequency. Therefore, an accurate SRF-EPI controller in the αβ stationary frame is established to achieve precise tracking accuracy. Moreover, the robustness, the harmonic rejection capability, and the influence of the control delay are investigated by the Nyquist stability criterion when the PVR-based AD method is adopted. Furthermore, grid voltage feed-forward and multiple PR controllers are integrated into the current loop to mitigate the current distortion introduced by the grid background distortion. In addition, the parameters design guidelines are presented to show the effectiveness of the proposed strategy. Finally, simulation and experimental results are provided to validate the feasibility of the proposed control approach.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.5
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• pp.62-70
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• 2007

In this paper, the boost Power Factor Correction(PFC) technique for Direct Torque Control(DTC) of brushless DC motor drive in the constant torque region is implemented on a TMS320F2812DSP. Unlike conventional six-step PWM current control, by properly selecting the inverter voltage space vectors of the two-phase conduction mode from a simple look-up table at a predefined sampling time, the desired quasi-square wave current is obtained, therefore a much faster torque response is achieved compared to conventional current control. Furthermore, to eliminate the low-frequency torque oscillations caused by the non-ideal trapezoidal shape of the actual back-EMF waveform of the BLDC motor, a pre-stored back-EMF versus position look-up table is designed. The duty cycle of the boost converter is determined by a control algorithm based on the input voltage, output voltage which is the dc-link of the BLDC motor drive, and inductor current using average current control method with input voltage feed-forward compensation during each sampling period of the drive system. With the emergence of high-speed digital signal processors(DSPs), both PFC and simple DTC algorithms can be executed during a single sampling period of the BLDC motor drive. In the proposed method, since no PWM algorithm is required for DTC or BLDC motor drive, only one PWM output for the boost converter with 80 kHz switching frequency is used in a TMS320F2812 DSP. The validity and effectiveness of the proposed DTC of BLDC motor drive scheme with PFC are verified through the experimental results. The test results verify that the proposed PFC for DTC of BLDC motor drive improves power factor considerably from 0.77 to as close as 0.9997 with and without load conditions.

• Molecules and Cells
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• v.45 no.7
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• pp.465-478
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• 2022

MicroRNAs (miRNAs) are a class of small non-coding RNAs that regulate the expression of target messenger RNA (mRNA) complementary to the 3' untranslated region (UTR) at the post-transcriptional level. Hsa-miR-422a, which is commonly known as miRNA derived from transposable element (MDTE), was derived from short interspersed nuclear element (SINE). Through expression analysis, hsa-miR-422a was found to be highly expressed in both the small intestine and liver of crab-eating monkey. AT-Rich Interaction Domain 5 B (ARID5B) was selected as the target gene of hsa-miR-422a, which has two binding sites in both the exon and 3'UTR of ARID5B. To identify the interaction between hsa-miR-422a and ARID5B, a dual luciferase assay was conducted in HepG2 cell line. The luciferase activity of cells treated with the hsa-miR-422a mimic was upregulated and inversely downregulated when both the hsa-miR-422a mimic and inhibitor were administered. Nuclear factor erythroid-2 (NF-E2) was selected as the core transcription factor (TF) via feed forward loop analysis. The luciferase expression was downregulated when both the hsa-miR-422a mimic and siRNA of NF-E2 were treated, compared to the treatment of the hsa-miR-422a mimic alone. The present study suggests that hsa-miR-422a derived from SINE could bind to the exon region as well as the 3'UTR of ARID5B. Additionally, hsa-miR-422a was found to share binding sites in ARID5B with several TFs, including NF-E2. The hsa-miR-422a might thus interact with TF to regulate the expression of ARID5B, as demonstrated experimentally. Altogether, hsa-miR-422a acts as a super enhancer miRNA of ARID5B by collaborating with TF and NF-E2.