• Title/Summary/Keyword: Faults

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A Current Differential Relaying Algorithm for Bus Protection Using a Compensating Algorithm of Secondary Currents of CTs (변류기 전류보상 알고리즘을 이용한 모선보호용 전류 차동계전 알고리즘)

  • Gang, Yong-Cheol;Yun, Jae-Seong;Kim, Dong-Yong
    • The Transactions of the Korean Institute of Electrical Engineers A
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    • v.49 no.9
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    • pp.446-450
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    • 2000
  • A conventional variable percentage current differential relaying algorithm for bus protection may misoperate for external faults with severe CT saturation and internal faults with high impedance. This paper proposes a percentage differential current relaying algorithm for bus protection combined with a compensating algorithm of secondary currents of CTs. Even though CTs are saturated and their secondary currents are severely distorted, the proposed relaying algorithm does not only misoperate for external faults with CT saturation but also detects the internal faults with high fault impedance. Thus, the method improves the sensitivity of the relays and does not require any counterplan for CT saturation.

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A Study on The Diagnosis of Broken Rotor Bars in Three Phase Squirrel-Case Induction Motor (3상 농형 유도전동기 회전자 바의 고장진단에 관한 연구)

  • Kim, K.W.;Kwon, J.L.;Lee, K.J.;Kim, W.G.
    • Proceedings of the KIEE Conference
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    • 2001.07b
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    • pp.635-637
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    • 2001
  • The faults of the squirrel cage induction motor is grew increasingly complex as the faults resulting in the shorting of a stator winding and the broken rotor bar or cracked rotor end ring, bearing faults, and so on. The users of electrical machines initially relied on simple protections such as over-current, over-voltage, earth-fault, etc. to ensure safe and reliable operation. but this method cause heavy financial losses and the threat of safety therefore it has now become very important to diagnose faults at there very inception. in this paper, we are going to discuss the detection method of broken rotor bar of squirrel cage induction motor by the motor current signal analysis(MCSA) and the opening terminal voltage signal analysis.

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A Study of a Voltage Sag Compensation Scheme on Loads by Using Flywheel Energy Storage system (플라이휠을 이용한 부하에의 순시전압강하 보상 방안 연구)

  • Lee, Han-Sang;Jang, Gil-Soo;Han, Sang-Cheul;Sung, Tae-Hyun;Han, Young-Hee
    • Proceedings of the KIEE Conference
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    • 2006.07a
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    • pp.321-322
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    • 2006
  • Faults on power systems are inevitable phenomena. These faults can be classified by two categories, temporary and permanent faults. Without distinction of fault types, the faults would induce several changes on power system such as transmission line trip. Especially, the most common phenomena which loads experience by the power system fault is voltage sag. Voltage sags mean that the bus voltage maintains under 0.9 p.u. of rating for several cycles, and they give serious effects to operation of load devices. To ensure proper operation of the load, the flywheel systems, one of the energy storage system, are suggested in this paper. This paper demonstrates the efficiency of flywheel energy storage system against voltage sag by PSCAD/EMTDC simulation.

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Universal Test Set Generation for Multi-Level Test of Digital CMOS Circuits (디지털 CMOS 회로의 Multi-Level Test를 위한 범용 Test Set 생성)

  • Dong Wook Kim
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.30A no.2
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    • pp.63-75
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    • 1993
  • As the CMOS technology becomes the most dominant circuit realization method, the cost problem for the test which includes both the transistor-level FET stuck-on and stuck-off faults and the gatelevel stuck-at faults becomes more and more serious. In accordance, this paper proposes a test set and its generation algorithm, which handles both the transistor-level faults and the gate-level faults, thus can unify the test steps during the IC design and fabrication procedure. This algorithm uses only the logic equation of the given logic function as the input resource without referring the transistor of gate circuit. Also, the resultant test set from this algorithm can improve in both the complexity of the generation algorithm and the time to apply the test as well as unify the test steps in comparing the existing methods.

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Fault analysis and testable desing for BiCMOS circuits (BiCMOS회로의 고장 분석과 테스트 용이화 설계)

  • 서경호;이재민
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.31A no.10
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    • pp.173-184
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    • 1994
  • BiCMOS circuits mixed with CMOS and bipolar technologies show peculiar fault characteristics that are different from those of other technoloties. It has been reported that because most of short faults in BiCMOS circuits cause logically intermediate level at outputs, current monitoring method is required to detect these faluts. However current monitoring requires additional hardware capabilities in the testing equipment and evaluation of test responses can be more difficult. In this paper, we analyze the characteristics of faults in BiCMOS circuit together with their test methods and propose a new design technique for testability to detect the faults by logic monitoring. An effective method to detect the transition delay faults induced by performance degradation by the open or short fault of bipolar transistors in BiCMOS circuits is presented. The proposed design-for-testability methods for BiCMOS circuits are confirmed by the SPICE simulation.

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A Study on the robust fault diagnosis and fault tolerant control method for the closed-loop control systems (폐회로 제어시스템의 강인한 고장진단 및 고장허용제어 기법 연구)

  • Lee, Jong-Hyo;Lyou, Joon
    • Journal of the Korea Institute of Military Science and Technology
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    • v.3 no.1
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    • pp.138-145
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    • 2000
  • This paper presents a robust fault diagnosis and fault tolerant control method for the control systems in closed-loop affected by unknown inputs or disturbances. The fault diagnostic scheme is based on the disturbance-decoupled state estimation using a 2-stage state observer for state, actuator bias and sensor bias. The estimated bias show the occurrence time, location and type of the faults directly. The estimated state is used for state feedback to achieve fault tolerant control against the faults. Simulation results show that the method has definite fault tolerant ability against actuator and sensor faults, moreover, the faults can be detected on-line, isolated and estimated simultaneously.

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A Study on High Impedance Fault Detection using Wavelet Transform and Neural-Network (웨이브릿 변환과 신경망 학습을 이용한 고저항 지락사고 검출에 관한 연구)

  • Hong, Dae-Seung;Ryu, Chang-Wan;Ko, Jae-Ho;Yim, Wha-Yeong
    • Proceedings of the KIEE Conference
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    • 1999.07b
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    • pp.856-858
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    • 1999
  • The analysis of distribution line faults is essential to the proper protection of power system. A high impedance fault(HIF) dose not make enough current to cause conventional protective device. It is well known that undesirable operating conditions and certain types of faults on electric distribution feeders cannot be detected by using conventional Protection system. This paper describes an algorithm using neural network for pattern recognition and detection of high impedance faults. Wavelet transform analysis gives the time-scale information. Time-scale representation of high impedance faults can detect easily and localize correctly the fault waveform.

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Test Pattern Generation for Detection of Sutck-Open Faults in BiCMOS Circuits (BiCMOS 회로의 Stuck-Open 고장 검출을 위한테스트 패턴 생성)

  • Sin, Jae-Hong
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.53 no.1
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    • pp.22-27
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    • 2004
  • BiCMOS circuit consist of CMOS part which constructs logic function, and bipolar part which drives output load. In BiCMOS circuits, transistor stuck-open faults exhibit delay faults in addition to sequential behavior. In this paper, proposes a method for efficiently generating test pattern which detect stuck-open in BiCMOS circuits. In proposed method, BiCMOS circuit is divided into pull-up part and pull-down part, using structural property of BiCMOS circuit, and we generate test pattern using set theory for efficiently detecting faults which occured each divided blocks.

Transient State Analysis of Faults Caused by Lightning Surge in Distribution Line (뇌서지에 의한 배전선로 고장 시 과도상태 분석)

  • Lim, Sung-Yong;Kim, Kyu-Ho
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.65 no.1
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    • pp.51-57
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    • 2016
  • This paper presents the voltage characteristics of the various faults after lightning surge hits the overhead grounding wire close to the transformer's secondary side. Based on the modeled distribution system, the cases of the various faults occurred by lightning surge are simulated using EMTP/ATPDraw and maximum overvoltage and RMS voltage according to the distances from the transformer are investigated. As a result, it is seen that the voltage characteristics of faults caused by lightning surge is different depending on the fault type and the voltage characteristics can be used to detect the fault type caused by lightning surge.

The Fault Diagnosis of a Transformer Using Neural Network and Transfer Function

  • Park, Byung-Koo;Kim, Jong-Wook;Kim, Sang-Woo;Park, Poo-Gyeon;Park, Tae-Joon
    • 제어로봇시스템학회:학술대회논문집
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    • 2001.10a
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    • pp.127.2-127
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    • 2001
  • A transformer is one of the most important elements in the power network. Transformer faults could cause costly repairs and be dangerous to personnel. To avoid this, its reliable operation has great significance and, therefore, the diagnosis system of the transformer is necessitated. The dissolved gas-in-oil analysis (DGA) is the worldwide popular method of detecting faults such as a hot spot or partial discharges inside the transformer. DGA, however, is not a reliable technique to identify aging phenomena and mechanical faults including insulation failure, inter-turn short, etc. To overcome the drawbacks of DGA, the transfer function method is used to identify effectively these kinds of the mechanical faults. The transformer has a unique transfer function independent of the shape of the input waveform, which can be evaluated through sweep test. This transfer function changes by winding ...

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