• Journal of Power Electronics
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• v.18 no.2
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• pp.558-572
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• 2018

In addition to its modular nature, a Hybrid Modular Multilevel Converter (HMMC) assembled from half-bridge and full-bridge sub-modules, is able to block DC faults with a minimum number of switching devices, which makes it attractive for high power applications. This paper introduces a control strategy based on the Root-Least Square (RLS) algorithm to estimate the capacitor voltages instead of using direct measurements. This action eliminates the need for voltage transducers in the HMMC sub-modules and the associated communication link with the central controller. In addition to capacitor voltage balancing and suppression of circulating currents, a fault tolerant control unit (FTCU) is integrated into the proposed strategy to modify the parameters of the HMMC controller. On advantage of the proposed FTCU is that it does not need extra components. Furthermore, a fault detection unit is adapted by utilizing a hybrid estimation scheme to detect sub-module faults. The behavior of the suggested technique is assessed using PSCAD offline simulations. In addition, it is validated using a real-time digital simulator connected to a real time controller under various normal and fault conditions. The proposed strategy shows robust performance in terms of accuracy and time response since it succeeds in stabilizing the HMMC under faults.

• Proceedings of the KSR Conference
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• 2008.06a
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• pp.572-578
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• 2008

As the railway transportation is getting faster and its operation speed has increased rapidly, its signal control has been complicated. For real time signal processing it is very important to prohibit any critical error from causing the system to malfunction. Therefore, handling complicated signals effectively while maintaining fault-tolerance capability is highly expected in modern railway transportation industry. In this paper, we suggest an SoC (Sytem-on-Chip) design method to integrate these complicated signal controlling mechanism with fault tolerant capability in a single chip. We propose an SoC solution which contains a high performance 32-bit embedded processor, digital filters and a PWM unit inside a single chip to implement ATO's, ATC's, ATP's and ATS's digital signal-processing units. We achieve an enhanced reliability against the calculation error by adding fault tolerance features to ensure the stability of each module.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.4
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• pp.22-30
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• 1992

A redundant control scheme which can maintain its tracking capability in the case of a controller failure is proposed for the industrial applications which need high reliability with fault-tolerance. It consists of two identical controllers and a switching mechanism which includes failure detection and reconfiguration algorithm. The new detection method against controller failure using fuzzy logic enables the detection of controller failures without failure assumptions through the instability of the failed controller. The failed controller is smoothly removed from the control loop by reducing time weight of the failed controller.

• Journal of Advanced Navigation Technology
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• v.14 no.2
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• pp.233-238
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• 2010

In this paper, we applied the forward and backward error recovery techniques to a reduced instruction set computer (risc) processor to develop two fault-tolerant processors, namely, fetch redundant risc (FRR) processor and a redundancy execute risc (RER) processor. To evaluate the fault-tolerance capability of three target processors, we developed the base risc processor, FRR processor, and RER processor in SystemC hardware description language. We performed fault injection experiment using the three SystemC processor models and the SystemC-based simulation fault injection technique. From the experiments, for the 1-bit transient fault, the failure rate of the FRR, RER, and base risc processor were 1%, 2.8%, and 8.9%, respectively. For the 1-bit permanent fault, the failure rate of the FRR, RER, and base risc processor were 4.3%, 6.5%, and 41%, respectively. As a result, for 1-bit fault, we found that the FRR processor is more reliable among three processors.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.2
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• pp.51-57
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• 2009

Ubiquitous sensor network is the communication environment where sensor nodes move freely and construct network to get the services from the system. So, it does not need fixed infrastructure and can easily be placed in unaccessible regions like war or calamity area. Wireless sensor network protocol has self-organizing capability, need to adapt topology change flexibly and also has technique that sensor nodes work cooperatively, because network disconnection is frequently occurred due to the active mobility of sensor nodes. In this paper, we design a cluster based fault-tolerant routing protocol for the efficient topology construction and to guarantee stable data transmission in USN. The performance of the proposed protocol is evaluated by an analytic model.

• Journal of Internet Computing and Services
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• v.4 no.6
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• pp.25-31
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• 2003

Multistage Interconnection networks (MIN) for the high performance computing and communications must be efficient and reliable. While a number of fault tolerance schemes have been developed, some of them are not efficient enough with respect to all evaluation measures or overheads of others are too significant. In this paper we develop a new efficient fault tolerant MIN which displays high reliability and fault tolerance capability using a simple structure. Structure and reliabilities of Enhanced Cube Network are evaluated and compared with previous designs to show the effectiveness of new design.

• Journal of international Conference on Electrical Machines and Systems
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• v.2 no.3
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• pp.269-274
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• 2013

Fault-tolerant capability, wide speed range and overload capability are required in electric motors used in electric vehicles. In this paper, based on the analysis of the all poles wound and alternate poles wound flux-switching permanent-magnet machines, an optimization method is studied to reduce torque ripple. The method takes account of both flux-leakage and cogging torque. The simulation result shows that the method can reduce the torque ripple effectively. This study lays the foundation for the further application of FSPM in electric vehicles.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.10
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• pp.3965-3982
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• 2015

Event detection is one of the key issues in many wireless sensor network (WSN) applications. The uncertainties that are derived from the instability of sensor node, measurement noise and incomplete sampling would influence the performance of event detection to a large degree. Many of the present researches described the sensor readings with crisp values, which cannot adequately handle the uncertainties inhered in the imprecise sensor readings. In this paper, a fault-tolerant event detection algorithm is proposed based on Dempster-Shafer (D-S) theory (also called evidence theory). Instead of crisp values, all possible states of the event are represented by the Basic Probability Assignment (BPA) functions, with which the output of each sensor node are characterized as weighted evidences. The combination rule was subsequently applied on each sensor node to fuse the evidences gathered from the neighboring nodes to make the final decision on whether the event occurs. Simulation results show that even 20% nodes are faulty, the accuracy of the proposed algorithm is around 80% for event region detection. Moreover, 97% of the error readings have been corrected, and an improved detection capability at the boundary of the event region is gained by 75%. The proposed algorithm can enhance the detection accuracy of the event region even in high error-rate environment, which reflects good reliability and robustness. The proposed algorithm is also applicable to boundary detection as it performs well at the boundary of the event.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2685-2688
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• 2003

A PC-based system for both monitoring and controlling SAUV is developed. The developed system is located on a ship and communicate with the SAUV through optical link through which the system sends motion command and receives video data, SSBL and Digital I/O data. The motion command includes velocity data and direction data. The overall system is developed with the intention of easy operation for operator and safe motion of SAUV. The easy operation is realized by GUI-based interface and the safe motion is realized by fault tolerant capability.

• The Transactions of the Korea Information Processing Society
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• v.4 no.9
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• pp.2259-2268
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• 1997

Multistage interconnection networks(MINs) provide a high-bandwidth communication between processors and/or memory modules in a cost-effective way. In this paper, we propose a class of multipath MINs, called the Augmented Modified Delta(AMD) network, and analyze its performance and reliability. The salient features of the AMD network include fault-tolerant capability, modular structure, and high performance, which are essential for real-time parallel/distributed processing environments. The class of the AMD network retains well-known characteristics of the Kappa network, but it's design procedure is more systematic. Like Delta networks, all the AMD networks are topologically equivalent with each other.