• Journal of IKEEE
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• v.25 no.2
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• pp.330-336
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• 2021

A typical way to reduce the number of hardware redundancy configurations is to implement them as analytical techniques for detecting, identifying and accepting failures with micro-controller. In this paper, one of the analytical techniques, the fault detection filter, is applied to aircraft turbofan engine system. The fault detection filter is a special type of observer that has the advantage of being able to determine the location of failures by maintaining a constant direction in the output space in the event of a particular failure. We present a single input/output dynamic system modeling of air turbine system in turbofan engine, a fault detection filter design, and simulation results applying it. Simulation results show that fault detection can be effectively applied as a sensitivity effect to the directionality of the detection filter.

• Journal of Advanced Navigation Technology
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• v.14 no.1
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• pp.87-92
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• 2010

The design of avionic embedded systems requires high-dependability. In this paper, we studied the dependability of the triple modular redundancy (TMR) hardware for highly reliable aviation embedded system. In order to evaluate the dependability of the base ARM processor and the TMR ARM processor, we developed the simulation model of the reduced ARM and TMR ARM processors and performed the simulation fault injection for the analysis of the dependability of the two targets. In the fault injection experiments, we calculated the error recovery rate of the two the processor models. From the experimental results, we could confirm that the reliability of the TMR ARM processor was greater than the single ARM processor by ten times in some cases.

• Journal of Advanced Navigation Technology
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• v.21 no.5
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• pp.491-500
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• 2017

This paper investigates a low cost dual modular redundancy system based on heartbeat which can be applied to traffic control signal system. Failure of the traffic control signal system can cause traffic confusion and traffic accidents. Therefore safety and reliability of traffic control should be secured using fault tolerance technology. To do this, we configured a redundant board using the open source hardware and the heartbeat technique of Linux HA. The function of the traffic signal control system was verified and the fault recovery time was measured using fault injection test. As a result of the test, the fault recovery time was confirmed to be less than 9 seconds on average, confirming that the reliability target time is satisfied. Based on the results of this study, it is expected that it can be applied to fields requiring high reliability systems such as aviation, space, and nuclear power embedded systems.

• Journal of Institute of Control, Robotics and Systems
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• v.12 no.12
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• pp.1241-1248
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• 2006

In high reliability systems for industrial network such as railway signal system, fieldbus protocols have been known to satisfy the real-time and fault tolerant requirements. But, the application of fieldbus has been limited due to the high cost of hardware and software, and the difficulty in interfacing with multi-vendor products. Therefore, as an alternative to fieldbus, the computer network technology, especially Ethernet(IEEE 802.3), is being adapted to the industrial network. In this paper, we propose a switched Ethernet based railway signal system because of its very promising prospect for industrial application due to the elimination of uncertainties in the network operation. In addition, we propose the redundancy architecture for the reliability of network components. More specifically, this paper presents an analytical performance evaluation of switched Ethernet for railway signal system, and shows experimental evaluation of redundancy architecture.

• ETRI Journal
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• v.31 no.3
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• pp.339-341
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• 2009

Built-in redundancy analysis (BIRA) is widely used to enhance the yield of embedded memories. In this letter, a new BIRA method for both high repair efficiency and small hardware overhead is presented. The proposed method performs redundancy analysis operations using the spare mapping registers with a covered fault list. Experimental results demonstrate the superiority of the proposed method compared to previous works.

• Journal of Advanced Navigation Technology
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• v.14 no.2
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• pp.233-238
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• 2010

In this paper, we applied the forward and backward error recovery techniques to a reduced instruction set computer (risc) processor to develop two fault-tolerant processors, namely, fetch redundant risc (FRR) processor and a redundancy execute risc (RER) processor. To evaluate the fault-tolerance capability of three target processors, we developed the base risc processor, FRR processor, and RER processor in SystemC hardware description language. We performed fault injection experiment using the three SystemC processor models and the SystemC-based simulation fault injection technique. From the experiments, for the 1-bit transient fault, the failure rate of the FRR, RER, and base risc processor were 1%, 2.8%, and 8.9%, respectively. For the 1-bit permanent fault, the failure rate of the FRR, RER, and base risc processor were 4.3%, 6.5%, and 41%, respectively. As a result, for 1-bit fault, we found that the FRR processor is more reliable among three processors.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.307-311
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• 2015

In this paper, we propose an efficient fault-recovery technique for CGRA (Coarse-Grained Reconfigurable Architecture) based multi-core architecture. The proposed technique is intra/inter-CGRA co-reconfiguration technique based on a ring-based sharing fabric (RSF) and it enables exploiting the inherent redundancy and reconfigurability of the multi-CGRA for fault-recovery. Experimental results show that the proposed approaches achieve up to 73% fault recoverability when compared with completely connected fabric (CCF).

• Journal of Korean Institute of Industrial Engineers
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• v.42 no.2
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• pp.151-164
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• 2016

In this paper, we deal with a risk analysis for an IPS (Integrated power system) and propose a simulation model combining the fault tree and event tree in order to estimate the system availability and risk level, together. Firstly, the basic information such as operational scenarios, physical structure, safety systems is explained in order to make the fault tree and event tree of the IPS. Next, we propose a discrete-event simulation model using a next-event time advance technique to advance the simulation time. Also the state transition and activity diagrams are explained to represent the relationship between the objects. By numerical examples, the redundancy allocation is considered in order to decrease the risk level of the IPS.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.2467-2470
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• 2003

In this paper, fault tolerant mechanisms are presented for a servo manipulator system designed to operate in a hot cell. A hot cell is a sealed and shielded room to handle radioactive materials, and it is dangerous for people to work in the hot cell. So, remote operations are necessary to handle radioactive materials in the hot cell. KAERI has developed a servo manipulator system to perform such remote operations. However, since electric components such as servo motors are weak to radiations, fault tolerant mechanisms have to be considered. For fault tolerance of the servo manipulator system, hardware and software redundancy have been considered. In case of hardware, radioactive resistant electric components such as cables and connectors have been adopted and motors driving a transport have been duplicated. In case of software, a reconfiguration algorithm accommodating one motor's failure has been developed. The algorithm uses redundant axis to recover the end effector's motion in spite of one motor's failure.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.14 no.1
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• pp.47-52
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• 2000

Redundant programmable logic controllers are used in practice with the aim of achieving a higher degree of availability or fault tolerance. Redundancy system is fault tolerant programmable logic controller for machine and plant. It is event synchronized master-standby system with a 2 channel(1-out-of-2) structure. A data link connects line the master to the standby controller.Fault tolerant systems should always be used when it is necessary to keep the probability of a total control system failure to a minimum. The objective of using high availability programmable logic controller is a reduction of losses of fault tolerant system are quickly compensated by the avoidance of loss of production.