• Proceedings of the KSR Conference
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• 2011.05a
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• pp.1618-1628
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• 2011

The Train Diagnostic and Control System(TDCS) has been equipped on the modern Metro Vehicle, Locomotive and High Speed Train. The main purpose of this system is to support the identification of train status by real-time, the fast action against such failure events during revenue service and the fast convenient maintenance processes. Some of newest TCMS, a kind of control and monitoring system, has participated in the main control functions such as pantograph up and down, powering and braking command and so on. But these kind of control functions of the high speed train which has the operating speed over 300km/h are conducted by the train electrical logic circuits. The KTX-I and KTX-II - the local high speed train, are the typical example. The next generation TDCS for the ongoing project of distributed high speed train(HEMU) is designing with the target to increase main train control functions, to increase the reliability/avalibility and to increase the convenient driving. This paper introduces the overall configurations and functions of the new generation TDCS.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.12
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• pp.1219-1223
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• 2010

This paper proposes a fast motion estimation algorithm based on motion speed and multiple initial center points. The proposed method predicts initial search points by means of the spatio-temporal neighboring motion vectors. A dynamic search pattern based on the motion speed and the predicted initial center points is proposed to quickly obtain the motion vector. Due to the usage of the spatio-temporal information and the dynamic search pattern, the proposed method greatly accelerates the search speed while keeping a good predicted image quality. Experimental results show that the proposed method has a good predicted image quality in terms of PSNR with less searching time comparing with the Full Search, New Three-Step Search, and Four-Step Search.

• Journal of Ocean Engineering and Technology
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• v.20 no.3 s.70
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• pp.82-87
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• 2006

An approach to model a high-speed monohull vessel is introduced. The high-speed monohull form belonging to the category of multihull is drawing new attention, due to the rapidly growing trend of fast passenger ships and military purpose. Multihull forms are much thinner in their overall shape, compared to those of the conventional commercial vessels. Moreover, the parent hull forms are not readily obtainable when a new design is intended, which makes it hard to perform various technical calculations in terms of hull optimization, hydrodynamic computation, structural design, and so forth. In this paper, a parametric technique is used to design a high-speed hull form. To model a hull form, NURBS (Non Uniform Rational B-Spline) representation is used. The goal of research is to provide a fast and convenient tool to design an initial hull form with fewer parameters available in the early design stage. The technique employed in this paper will be applied to the design of multihull forms, such as catamaran, trimaran, and semi-swath.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.30 no.6
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• pp.21-30
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• 2002

A preconditioned Navier-Stokes code was parallelized by the domain decomposition technique, and the accuracy of the parallelized code was verified through a comparison with the result of a sequential code and experimental data. Parallel performance of the code was examined on a Myrinet based PC-cluster and a Fast-Ethernet system. Speed-up ratio was examined as a major performance parameter depending on the number of processor and the network communication topology. In this test, Myrinet system shows a superior parallel performance to the Fast-Ethernet system as was expected. A test for the dependency on problem size also shows that network communication speed in a crucial factor for parallel performance, and the Myrinet based PC-cluster is a plausible candidate for high performance parallel computing system.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.52-55
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• 1997

This paper discusses an automatic visual-servoing system, in which a laser and a CCD camera are used for imaging the pattern of joint groove. The algorithm used here is simple and robust to find out the gap width and gap center. As a consequence, the speed of algorithm is very fast and optimized. A feature of this system is that it processes only by summing the vertical line and horizontal line of screen without any image preprocessing in order to get the energy information of lines alternatively. It is practical and useful for the system requiring a fast process time of vision.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.45-48
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• 2005

In this paper, we propose a new fast running FIR filter structure that improves the convergence speed of adaptive signal processing and reduces the computational complexity. The proposed filter is applied to wavelet based adaptive algorithm. Actually we compared the performance of the proposed algorithm with other algorithm using computer simulation of adaptive noise canceler based on synthesis speech. As the result, We know the proposed algorithm is prefer than the existent algorithm.

• Proceedings of the Korea Information Processing Society Conference
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• 2007.05a
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• pp.860-861
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• 2007

The Pulse Coupling Oscillator (PCO) is a synchronicity model inspired by nature. However, the PCO model has some limitations. The Fast PCO model is proposed in this paper. It addresses the problem of the phase swing actions in the original PCO model. Benefits are the fast synchronicity speed and associated energy saving.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.91-94
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• 2000

This paper introduces the design of low-power, fast-locking delay locked-loop using complementary pass transistor logic(CPL). Low-power design has become one of the most important in the modem VLSI application. CPL has the advantage of fast speed, high density, and low power with signal buffering between stages. Based on this analysis, we concluded that the I/O performance can be beyond 500㎒, 2-poly, 2-metal 0.65$\mu\textrm{m}$, 3.3V supply.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.5
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• pp.661-670
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• 1995

This paper presents a fast massively parallel automatic test pattern generator for digital combinational logic circuits using neural networks. Automatic test pattern generation neural network(ATPGNN) evolves its state to a stable local minima by exchanging messages among neural network modules. In preprocessing phase, we calculate the essential assignments for the stuck-at faults in fault list by adopting dominator concept. It makes more neurons be fixed and the system speed up. Consequently. fast test pattern generation is achieved. Test patterns for stuck-open faults are generated through getting initialization patterns for the obtained stuck-at faults in the corresponding ATPGNN.

• Proceedings of the Acoustical Society of Korea Conference
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• 1991.06a
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• pp.38-41
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• 1991

RLS algorithms are required for applications to adaptive line enhancers, adaptive equalizers for voiceband telephone and HF modems, and wide-badn digital spectrum mobile raio in which their convergence time and tracking speed are significant. The fast QR RLS algorithm satisfies above the requirements. Its computational complexity is linearly proportional to the tap number of a filter, N and its performance remains numerically stable. From the result of simumulation, the fast QR RLS algorithm represented Cioffi is better than gradient based algorithm in its initial performance when being applied to an adaptive line enhancer for cancelling noise.