• Journal of Korean Orthopaedic Sports Medicine
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• v.5 no.1
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• pp.63-68
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• 2006

Purpose: To assess the effectiveness of the Locking compression plate (LCP) after open reduction for the treatment of the displaced clavicular shaft fracture, the clinical and radiologic outcome of the patients who were managed with the LCP for internal fixation after open reduction has been analyzed. Materials and Methods: We reviewed 26 cases with a displaced clavicular shaft fracture treated by internal fixation using Locking compression plate after open reduction between May 2003 and November 2004. The patients were followed up for at least six months period, and final postoperative outcome was evaluated using clinical results based on Kang's criteria, radiologic signs of fusion. Results: All fractures united by an average of 9.3 weeks without delayed union and showed fast recovery of motion fraction and shoulder function. In addition,24 cases without the fractures of proximal humerus recovered to normal range of shoulder notion within 2.9 weeks. Clinically, according to Kang's criteria, the outcome was good or better in 22 patients. The complications included shoulder joint dysfunction in two cases and keloid formation in one case, and no other complications were observed. Conclusion: The internal fixation using LCP for the treatment of displaced clavicular shaft fracture is a safe, reliable method of treatment, with few complications, and offers rapid recovery of shoulder joint function and bone union.

• Journal of IKEEE
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• v.23 no.3
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• pp.800-804
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• 2019

This paper presents a dual-loop sub-sampling digital PLL for a 2.4 GHz IoT applications. The PLL initially performs a divider-based coarse lock and switches to a divider-less fine sub-sampling lock. It achieves a low in-band phase noise performance by enabling the use of a high resolution time-to-digital converter (TDC) and a digital-to-time converter (DTC) in a selected timing range. To remove the difference between the phase offsets of the coarse and fine loops, a phase offset calibration scheme is proposed. The phase offset of the fine loop is estimated during the coarse lock and reflected in the coarse lock process, resulting in a smooth transition to the fine lock with a stable fast settling. The proposed digital PLL is designed by SystemVerilog modeling and Verilog-HDL and fully verified with simulations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1153-1157
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• 2004

This paper describes a new programmable DLL_based frequency synthesizer. Generally, PLLs have been used for frequency synthesis. Inherent fast locking DLLs are also used for frequency synthesis. However, DLL needs a frequency multiplier for various frequencies. A conventional frequency multiplier used in DLL has a restriction in which a multiple is fixed. However, the proposed DLL can generate clocks which are from 6 times to 10 times of the reference clock. Frequency range of the proposed DLL is from 600MHz to 1GHz. The idea has been confirmed by HSPICE simulations in a $0.35-\mu\textrm{m}$ CMOS process.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 2003.10a
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• pp.3-17
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• 2003

This paper deals with the problems and their possible solutions in the development of finite element for analysis of shell. Based on these solution schemes, a series of flat shell elements are established which show no signs of membrane locking and other defects even though the coarse meshes are used. In the element formulation, non-conforming displacement modes are extensively used for improvement of element behaviors. A number of numerical tests are performed to prove the validity of the solutions to the problems involved in establishing a series of high performance flat shell elements. The test results reveal among others that the high accuracy and fast convergence characteristics of the elements are obtainable by the use of various non-conforming modes and that the ‘Direct Modification Method’ is a very useful tool for non-conforming elements to pass the patch tests. Furthermore, hierarchical and higher order non-conforming modes are proved to be very efficient not only to make an element insensitive to the mesh distortion but also to remove the membrane locking. Some numerical examples are solved to demonstrate the validity and applicability of the presented elements to practical engineering shell problems.

• Nuclear Engineering and Technology
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• v.54 no.8
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• pp.2852-2858
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• 2022

A proton therapy facility is under development at Huazhong University of Science and Technology (HUST). To meet the need for fast energy changes during treatments, a beamline control system (BCS) has been designed and implemented. The BCS coordinates and controls various beamline devices by adopting a distributed architecture divided into three layers: the client, server, and device layers. Among these, the design of the server layer is the key to realize fast energy changes. The server layer adopts the submodule programming paradigm and optimizes the data interface among modules, allowing the main workflow to be separated from the device workflow and data. Furthermore, this layer uses asynchronous, multithreaded, and thread-locking methods to improve the system's ability to operation efficiently and securely. Notably, to evaluate the changing energy status over time, a dynamic node update method is adopted, which can dynamically adjust the update frequency of variable nodes. This method not only meets the demand for fast updates on energy changes but also reduces the server's communication load in the steady state. This method is tested on a virtual platform, and the results are as expected.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.506-517
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• 2015

This paper presents a 1.248 Gb/s - 2.918 Gb/s low-power receiver MIPI-DigRF M-PHY with a fully digital frequency detection loop. MIPI-DigRF M-PHY should be operated in a very short training time which is $0.01{\mu}s$ the for HS-G2B mode. Because of this short SYNC pattern, clock and data recovery (CDR) should have extremely fast locking time. Thus, the quarter rate CDR with a fully digital frequency detection loop is proposed to implement a fast phase tracking loop. Also, a low power CDR architecture, deserializer and voltage controlled oscillator (VCO) are proposed to meet the low power requirement of MIPI-DigRF M-PHY. This chip is fabricated using a $0.11{\mu}m$ CMOS process, and the die area is $600{\mu}m{\times}250{\mu}m$. The power consumption of the receiver is 16 mW from the supply voltage of 1.1 V. The measured lock time of the CDR is less than 20 ns. The measured rms and peak jitter are $35.24ps_{p-p}$ and $4.25ps_{rms}$ respectively for HS-G2 mode.

• Structural Engineering and Mechanics
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• v.23 no.5
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• pp.487-504
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• 2006

Several new versatile two-dimensional p-version finite elements are developed. The element matrices are integrated analytically to guarantee the accuracy and monotonic convergence of the predicted solutions of the proposed p-version elements. The analysis results show that the convergence rate of the present elements is very fast with respect to the number of additional Fourier or polynomial terms in shape functions, and their solutions are much more accurate than those of the linear finite elements for the same number of degrees of freedom. Additionally, the new p-version plate elements without the reduced integration can overcome the shear locking problem over the conventional h-version elements. Using the proposed p-version elements with fast convergent characteristic, the elasto-plastic impact of the structure attached with the absorber is simulated. Good agreement between the simulated and experimental results verifies the present p-version finite elements for the analyses of structural dynamic responses and the structural elasto-plastic impact. Further, using the elasto-plastic impact model and the p-version finite element method, the absorber of the T structure on the Qiantang River is designed for its collision protection.

• Structural Engineering and Mechanics
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• v.6 no.8
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• pp.921-937
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• 1998

A new four-node degenerated shell element with drilling degrees of freedom (DOF) is proposed. Allman-type displacement approximation is incorporated into the formulation of degenerated shell elements. The approximation improves in-plane performance and eliminates singularities of system matrices resulted from DOF deficiency. Transverse shear locking is circumvented by introducing assumed covariant shear strains. Two kinds of penalty energy are considered in the formulation for the purpose of suppressing spurious modes and representing true drilling rotations. The proposed element can be applied to almost all kinds of shell problems including composite laminated shell structures and folded shell structures. Numerical examples show that the element is of good accuracy and of reasonably fast convergence rate.

• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.456-458
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• 1997

The phase-lock technique is applied to a three-phase semi-bridge type battery charger system. Using an inner fast dynamic loop, the phase-locked voltage control (PLVC) technique of three-phase semi-bridge converter is proposed to give a frequency synchronism and to reduce the subharmonics due to the unbalance of transformer or power line. To protect the power devices, the two stage soft-start, function with softly locking the phase and softly increasing the current is presented. As limiting the reference voltage of the inner voltage control loop, muti-lock phenomena are removed on the PLVC loop. A current limit function is also proposed to limit the current of battery and converter. The proposed controller is confirmed through experiment results.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.697-699
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• 2017

A novel structure of phase locked loop (PLL) which has small size with D Flip-Flop and sub charge pump has been proposed. The area of loop filter usually occupying the larger portion of the chip is minimized using a single small capacitor. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.