• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.1159-1162
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• 2004

A modeling of the nucleation and dynamical behavior of defects from an inhomogeneous surface configuration using fast Q-tensor method is realized. On modeling the defect nucleation and dynamics, A fast Q-tensor method is applied. From the numerical modeling, we confirmed that surface inhomogeneity which makes strong strain energy in the local liquid crystal director field could cause defects. Experimental result has compared with numerical modeling in order to verify the simulation of the defect nucleation.

• Electronics and Telecommunications Trends
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• v.18 no.5 s.83
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• pp.19-26
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• 2003

Mobile IPv6는 IPv6에 기반한 IP 이동성을 제공하기 위하여 IETF에서 현재 작업중인 프로토콜로서 올 연말쯤 RFC 문서화 될 전망이다. 하지만 실제로 Mobile IPv6를 구현하고 테스트해 본 결과 handover시 여러 가지 문제점이 대두되었고, 그 중의 하나가 handover delay가 서비스에 지장을 줄 정도로 크다는 것이었다. 본 고에서는 Mobile IPv6의 handover delay를 줄이기 위해서 IETF Mobileip WG에서 진행중에 있는 다양한 fast handover 기법에 대하여 살펴 본다. Mobile IPv6는 Mobile IPv4와 마찬가지로 실제 상용망에서 많이 활용되고 쓰이기 위해서는 fast handover나 QoS 지원 같은 서비스 품질을 지원하여야 할 것으로 전망된다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.10
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• pp.1617-1623
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• 1989

The introduction of the fast Fourier transform(FFT),an efficient computational algorithm for the discrete Fourier transform(DFT) by Cooley and Tukey(1965), has brought to the limelight various other discrete transforms. Some of the analog functions from which these transforms have been derived date back to the early 1920's, for example, Walsh functions (Walsh, 1923) and Hadamard Transform(Enomoto et al, 1965). Fast algorithms developed for the forward transform are equally applicable, exept for minor changes, to the inverse transform. In this paper, we present a simple pipelined Hadamard matrix(HM) which is used to develop a fast algorithm for the Hadamard Processor (HP). The Fast Hadamard Transform(FHT) can be derived using matrix partitioning techniques. The HP system is incorporated through a modular design which permits tailoring to meet a wide range of video data link applications. Emphasis has been placed on a low cost, a low power design suitable for airbone system and video codec.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.12
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• pp.83-89
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• 1996

The electrochemical spike oscillations at the nickel (Ni) electrode/(0.05M KHC$_{8}$H$_{4}$O$_{4}$) buffer solution (pH 9) interface have been studied using voltammetric and chronoamperometric methods. The nature of the periodic cathodic current spikes is the activation controlled currents due to the hydrogen evolution reaction and depends onthe fractioanl surface coverage of the adsorbed hydrogen intermediate or the cathodic potential. There is two kinds of the waveforms corresponding to two kinds of the cathodic current spike oscillations. The widths, periods, and amplitudes of the cathodic current spikes are 4 ms or 5ms, 151 ms or 302 ms, and < 30 mA or < 275 mA, respectively. The fast discharge and recombination reaction steps are 1.5 times and twice and faster than the slow discharge and recombination reaction steps. The fast and slow discharge and recombination reaction steps are 1.5 times and twice faster than the slow discharge and recombination reaction steps. The fast and slow discharge and recombination reactions corresponding to the fast and slow adsorption sites at the Ni cathode.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.810-817
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• 2014

An on-chip current sensor with fast response time for the peak-current-mode buck regulator is proposed. The initial operating points of the peak current sensor are determined in advance by the valley current level, which is sensed by a valley current sensor. As a result, the proposed current sensor achieves a fast response time of less than 20 ns, and a sensing accuracy of over 90%. Applying the proposed current sensor, the peak-current-mode buck regulator for the mobile application is realized with an operating frequency of 2 MHz, an output voltage of 0.8 V, a maximum load current of 500 mA, and a peak efficiency of over 83%.

• Journal of Power Electronics
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• v.4 no.2
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• pp.87-95
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• 2004

A new fast-response high-current clamp DC-DC converter circuit design is presented that will meet the requirements and features of the new generation of microprocessors and digital systems. The clamp in the proposed converter amplifies the current in case of severe load changes and is able to produce high slew rate of output current and capability to keep constant the output voltage. This proposed high-current clamp technique is theoretically loss less, low cost and easy to implement with simple control scheme. This is modified from a basic buck topology by replacing the output inductor with two magnetically coupled inductors. Inductors are difference in inductance, one has large inductance and other has small inductance. The inductor with small inductance will take over the output inductor during fast load transient. It speedup the output current slew rate and reduce the output voltage drop in the case of heavy burden load changes.

• Journal of Power Electronics
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• v.13 no.6
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• pp.991-999
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• 2013

In this paper, a fast transient buck converter using hysteresis PWM control is presented. The proposed control method is based on hysteresis control of the capacitor C voltage. This offers a faster transient response to meet the challenges of the power supply requirements for fast dynamic input and load changes. It also provides better stability and solves the compensation problem of the error amplifier in conversional voltage PWM control. Finally, the steady-state and dynamic operation of the proposed control method are analyzed and verified by simulation and experimental results.

• ETRI Journal
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• v.44 no.3
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• pp.379-388
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• 2022

This study proposes a novel low-complexity algorithm for computing inverse fast Fourier transform (IFFT)/fast Fourier transform (FFT) operations in binary phase shift keying-modulated orthogonal frequency division multiplexing (OFDM) communication systems without requiring any twiddle factor multiplications. The peak-to-average power ratio (PAPR) reduction capacity of an efficient PAPR reduction technique, that is, H-SLM method, is evaluated using the proposed IFFT algorithm without any complex multiplications, and the impact of oversampling factor for the accurate calculation of PAPR is analyzed. The power spectral density of an OFDM signal generated using the proposed multiplierless IFFT algorithm is also examined. Moreover, the bit-error-rate performance of the H-SLM technique with the proposed IFFT/FFT algorithm is compared with the classical methods. Simulation results show that the proposed IFFT/FFT algorithm used in the H-SLM method requires no complex multiplications, thereby minimizing power consumption as well as the area of IFFT/FFT processors used in OFDM communication systems.

• The Transactions of the Korean Institute of Power Electronics
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• v.21 no.5
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• pp.373-380
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• 2016

In this paper, a 50-kW high-efficiency modular fast charger for both electric vehicle (EV) and neighborhood electric vehicle (NEV) is proposed. The proposed fast charger consists of five 10-kW modules to achieve fault tolerance, ease of thermal management, and reduce component stress. Three-level topologies for both AC-DC and DC-DC converters are employed to use 600V MOSFET, resulting in ease of component selection and increase in switching frequency. The proposed three-level DC-DC converter with coupled inductor and its hybrid switching method can reduce the circulating current under wide output voltage range. A 50-kW prototype of the proposed fast charger was developed and tested to verify the validity of the proposed concept. Experimental results show that the proposed fast charger achieves a rated efficiency of 95.2% and a THD of less than 3%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.83-88
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• 2005

We propose the design method for the VLSI architecture of FNNPDS combined PDS(partial distance search) and FNNS(fast nearest neighbor search), which are used to fast encoding in vector quantization, and obtain the results that FNNPDS(fast nearest neighbor partial distance search) is faster method than the conventional methods by simulation. In simulations, we investigate timing diagrams described searching time of the nearest codevector for an input vector, and compare the average clock cycles per input vector for Lena and Peppers images. According to the result of simulations, the number of the clock cycle of FNNPDS was reduced to $79.2\%\~11.7\%$ as compared with the number using the conventional techniques.