• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.205-208
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• 2002

An existing ATM switch fabric uses VPI(Virtual Path Identifier) and VCI(Virtual Channel Identifier) information to route ATM cell. But AAL type 2 switch which efficiently processes delay-sensitive, low bit-rate data such as a voice routes the ATM cell by using CID(Channel Identification) field in addition to VPI and VCI. In this paper, we research the AAL type 2 switch that performs the process of CPS packet. The Receive unit extracts the CPS packet from the inputted ATM cell. The designed receive unit consists of input FIFO, r)( status table, CAM(Content Addressable Memory), new CID table and partial packet memory. Also the designed receive unit supports the PCI interface with host processor. The receive unit is implemented in Xilinx FPGA and operates at 72MHz.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.944-947
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• 2002

We implemented a cryptoprocessor with a on-the-fly key scheduler which performs forward key scheduling for encryption and reverse key scheduling for decryption. This scheduler makes the fast generation of the key value and eliminates the memory for software key scheduler. The 128-bit Rijndael processor is implemented based on the proposed architecture using Verilog-HDL and targeted to Xilinx XCV1000E FPGA device. As a result, the 128-bit Rijndael operates at 38.8MHz with on-the-fly key scheduler and consumes 11 cycles for encryption and decryption resulting in a throughput of 451.5Mbps

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.224-227
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• 1999

This paper presents a design of the real-time preprocessor for CMOS image sensor suitable to the digital camera applications. CMOS image sensor offers some advantages in on-chip integration, system power reduction, and low cost. However, it has a lower-quality image than CCDs. We describe an image enhancement algorithm, which includes color interpolation, color correction, gamma correction, sharpening, and automatic exposure control, to compensate for this disadvantage, and present its efficient hardware architecture to implement on the real-time processor. The presented real-time preprocessor was designed using VHDL, and it contains about 19.2K logic gates. We also implement our system on FPGA chips in order to provide the real-time adjustment and it was successfully tested.

• 전기학회논문지
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• 제59권10호
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• pp.1923-1928
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• 2010

The IEC 61850 protocol proposed for the interoperability between IEDs(intelligent electronic devices) adopts the prioritized switched ethernet as its communication channel because substation bus is utilized to exchange both real-time and non real-time messages. The prioritized switched ethernet uses IEEE 802.1Q/p QoS(Quality of Service) in addition to IEEE 802.3 ethernet to enhance the real-time characteristics. However, IEEE 802.1Q/p QoS has priority-blocking problem that occurs when higher-priority frame transmission request during lower-priority frame transmission. To resolve this problem, this paper proposes P(Preemptive)-Ethernet. P-Ethernet uses the modified IEEE 802.1Q/p frame format and new priority preemption mechanism. This paper also implements P-Ethernet controller using FPGA (Virtex-4) and MicroBlaze processor. From the implementation results, P-Ethernet controller shows a improved latency and jitter of transmission period compare to the normal ethernet controller.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 2003년도 춘계 학술대회 학술발표 논문집
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• pp.299-302
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• 2003

대용량의 퍼지데이터를 처리하기 위한 퍼지제어 시스템의 가장 큰 과제는 퍼지추론 및 비퍼지화 단계에서의 수행속도의 개선이다. 본 논문에서는 퍼지제어기의 속도 향상을 위해 [0, 1]사이의 실수값을 갖는 퍼지 소속 함수값을 정수형 격자(pixel)에 매핑시켜 정수형 퍼지 소속함수값만을 가지고 퍼지연산을 하는 정수형 퍼지제어기법을 적용한 고속이 정수 연산을 수행하는 퍼지 프로세서와 주변제어 시스템을 FPGA로 설계하여 기존 퍼지제어 시스템에 비해 매우 빠른 실시간 고속퍼지 제어시스템을 구현한다.

• 디지털산업정보학회논문지
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• 제5권4호
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• pp.127-137
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• 2009

This paper is proposed that in-output Digital module is acquired a vibration signal of a rotating machinery by Data Acquisition System. The module is designed to get ride of nose through low pass filter on the vibration signal from sensors and set the gain value for being able to sampling AC to DC, and also the sampled data by sampler and the conversed data by DIP/FPGA is supplied to the analyzer for analysis at a software tool. The DIP(Digital Signal Processor) of the Digital input/output Board makes Average voltage, Peak to Peak voltage, RMS(Root Mean Square) and Gap voltage, also FFT(Fast Fourier Transform) for rotating vibration diagnosis.

• 디지털산업정보학회논문지
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• 제9권1호
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• pp.95-102
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• 2013

This paper covers nulling algorithm. In this algorithm, we assume that nulling points are already known. In general, nulling algorithm using matrix equation was utilized. But, this algorithm is pointed out that computational complexity is disadvantage. So, we choose gradient method to reduce the computational complexity. In order to further reduce the computational complexity, we propose approximate gradient method using characteristic of trigonometric functions. The proposed method has same performance compared with conventional method while having half the amount of computation when the number of antenna and nulling point are 20 and 1, respectively. In addition, we could virtually eliminate the trigonometric functions arithmetic. Trigonometric functions arithmetic cause a big problem in actual implementation like FPGA processor(Field Programmable gate array). By utilizing the above algorithm in a multi-cell environment, beamforming gain can be obtained and interference can be reduced at same time. By the above results, the algorithm can show excellent performance in the cell boundary.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1551-1554
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• 2002

In this paper, the hardware implementation of the RSA public-key cryptographic algorithm is presented. The RSA cryptographic algorithm is depends on the computation of repeated modular exponentials. The Montgomery algorithm is used and modified to reduce hardware resources and to achieve reasonable operating speed for smart card. An efficient architecture for modular multiplications based on the array multiplier is proposed. We have implemented a 10240it RSA cryptographic processor based on proposed scheme in IESA system developed for smart card emulating system. As a result, it is shown that proposed architecture contributes to small area and reasonable speed for smart cards.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.629-630
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• 2006

This paper presented a hardware implementation of ARIA, which is Korean standard block ciphering algorithm. In this work, we proposed a improved architecture based on pipeline structure and confirmed that the design operates in a clock frequency of 101.7MHz and in throughput of 957Mbps in Xilinx FPGA XCV-1600E.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 통신소사이어티 추계학술대회논문집
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• pp.382-385
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• 2003

Introduction of digital broadcasting service does not only mean the change of information transmission method but also the change of total broadcasting system. In past day, Television was only received one-sided information from broadcasting station, but digital broadcasting means that digital television becomes the most important means of information transmission by the introduction of new programming, lots of channels, data service, multi communication. In the age of the digital broadcasting, the recording and replay medium's interest is getting higher. The medium is able to record more than 24 hours' digital broadcasting programs without additional tapes. In this paper the recording and replay device using HDD was implemented and device driver based on linux was programmed. It has Intel PXA250 processor and hard disk is used as storage equipment. And transport Stream is saved on hard disk through PXA250's data bus. FIFO is added to solve the different saving speed and FPGA is also added to display the saved data.