• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.449-450
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• 2008

In this paper, we present the design of a system on a chip(SoC) based on Powerline Communication for Power-IT. The SoC deals with power information obtained from analog to digital converter and transmits this data via powerline. We integrate main processor, ADC and PLC function into a chip. Also a FPGA-based emulation system is introduced to evaluate a proposed SoC architecture.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.4
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• pp.371-376
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• 2004

Distributed Network Protocol Version 3.0 (DNP3.0) is the communication protocol developed for the interoperability between a RTU and a central control station of SCADA in the power utility industry. In this paper DNP3.0 is implemented by using HDL with FPGA and C program on Hitachi H8/532 processor. DNP3.0 is implemented from physical layer to network layer in hardware level to reduce the computing load on a CPU. Finally, the ASIC for DNP3.0 has been manufactured from Hynix Semiconductor. The commercial feasibility of the hardware through the communication test with ASE2000 and DNP Master Simulator is performed. The developed protocol becomes one of IP, and can be used to implement SoC for the terminal device in SCADA systems. Also, the result can be applicable to various industrial controllers because it is implemented in HDL.

• Journal of Institute of Control, Robotics and Systems
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• v.18 no.5
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• pp.479-486
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• 2012

In this paper, a ranging system is proposed that is able to measure 360 degree omnidirectional distances to environment objects. The ranging system is based on the structured light imaging system with catadioptric omnidirectional mirror. In order to make the ranging system robust against environmental illumination, efficient structured light image processing algorithms are developed; sequential integration of difference images with modulated structured light and radial search based on Bresenham line drawing algorithm. A dedicated FPGA image processor is developed to speed up the overall image processing. Also the distance equation is derived in the omnidirectional imaging system with a hyperbolic mirror. It is expected that the omnidirectional ranging system is useful for mapping and localization of mobile robot. Experiments are carried out to verify the performance of the proposed ranging system.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.205-208
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• 2002

An existing ATM switch fabric uses VPI(Virtual Path Identifier) and VCI(Virtual Channel Identifier) information to route ATM cell. But AAL type 2 switch which efficiently processes delay-sensitive, low bit-rate data such as a voice routes the ATM cell by using CID(Channel Identification) field in addition to VPI and VCI. In this paper, we research the AAL type 2 switch that performs the process of CPS packet. The Receive unit extracts the CPS packet from the inputted ATM cell. The designed receive unit consists of input FIFO, r)( status table, CAM(Content Addressable Memory), new CID table and partial packet memory. Also the designed receive unit supports the PCI interface with host processor. The receive unit is implemented in Xilinx FPGA and operates at 72MHz.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.944-947
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• 2002

We implemented a cryptoprocessor with a on-the-fly key scheduler which performs forward key scheduling for encryption and reverse key scheduling for decryption. This scheduler makes the fast generation of the key value and eliminates the memory for software key scheduler. The 128-bit Rijndael processor is implemented based on the proposed architecture using Verilog-HDL and targeted to Xilinx XCV1000E FPGA device. As a result, the 128-bit Rijndael operates at 38.8MHz with on-the-fly key scheduler and consumes 11 cycles for encryption and decryption resulting in a throughput of 451.5Mbps

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.224-227
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• 1999

This paper presents a design of the real-time preprocessor for CMOS image sensor suitable to the digital camera applications. CMOS image sensor offers some advantages in on-chip integration, system power reduction, and low cost. However, it has a lower-quality image than CCDs. We describe an image enhancement algorithm, which includes color interpolation, color correction, gamma correction, sharpening, and automatic exposure control, to compensate for this disadvantage, and present its efficient hardware architecture to implement on the real-time processor. The presented real-time preprocessor was designed using VHDL, and it contains about 19.2K logic gates. We also implement our system on FPGA chips in order to provide the real-time adjustment and it was successfully tested.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.10
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• pp.1923-1928
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• 2010

The IEC 61850 protocol proposed for the interoperability between IEDs(intelligent electronic devices) adopts the prioritized switched ethernet as its communication channel because substation bus is utilized to exchange both real-time and non real-time messages. The prioritized switched ethernet uses IEEE 802.1Q/p QoS(Quality of Service) in addition to IEEE 802.3 ethernet to enhance the real-time characteristics. However, IEEE 802.1Q/p QoS has priority-blocking problem that occurs when higher-priority frame transmission request during lower-priority frame transmission. To resolve this problem, this paper proposes P(Preemptive)-Ethernet. P-Ethernet uses the modified IEEE 802.1Q/p frame format and new priority preemption mechanism. This paper also implements P-Ethernet controller using FPGA (Virtex-4) and MicroBlaze processor. From the implementation results, P-Ethernet controller shows a improved latency and jitter of transmission period compare to the normal ethernet controller.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2003.05a
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• pp.299-302
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• 2003

In fuzzy control systems having large volumes of fuzzy data. one of the important problems is the improvement of execution speed in the fuzzy inference and defuzzification stages. In this paper, to improve the speedup of fuzzy controllers, we use an integer line mapping algorithm to convert [0, 1] real values in the fuzzy membership functions to integer pixels. U sing this, we propose a real-time high-speed fuzzy control system and implement a fast fuzzy processor and control system using FPGAs.

• Journal of Korea Society of Digital Industry and Information Management
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• v.5 no.4
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• pp.127-137
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• 2009

This paper is proposed that in-output Digital module is acquired a vibration signal of a rotating machinery by Data Acquisition System. The module is designed to get ride of nose through low pass filter on the vibration signal from sensors and set the gain value for being able to sampling AC to DC, and also the sampled data by sampler and the conversed data by DIP/FPGA is supplied to the analyzer for analysis at a software tool. The DIP(Digital Signal Processor) of the Digital input/output Board makes Average voltage, Peak to Peak voltage, RMS(Root Mean Square) and Gap voltage, also FFT(Fast Fourier Transform) for rotating vibration diagnosis.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.1
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• pp.95-102
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• 2013

This paper covers nulling algorithm. In this algorithm, we assume that nulling points are already known. In general, nulling algorithm using matrix equation was utilized. But, this algorithm is pointed out that computational complexity is disadvantage. So, we choose gradient method to reduce the computational complexity. In order to further reduce the computational complexity, we propose approximate gradient method using characteristic of trigonometric functions. The proposed method has same performance compared with conventional method while having half the amount of computation when the number of antenna and nulling point are 20 and 1, respectively. In addition, we could virtually eliminate the trigonometric functions arithmetic. Trigonometric functions arithmetic cause a big problem in actual implementation like FPGA processor(Field Programmable gate array). By utilizing the above algorithm in a multi-cell environment, beamforming gain can be obtained and interference can be reduced at same time. By the above results, the algorithm can show excellent performance in the cell boundary.