• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.214-217
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• 2003

In this paper, we deal with implementing design for a correlator access code generator module which they are used for setting up a connection between units, a packet decision, a clock syncronization, by FPGA. The orrelator module which is composed of the Wallace Tree's CSA and threshold value decision device decides useful a packet and syncronizes a clock, after it correlates an input signal of 1 Mbps transmission rate by a sliding window. An access code generator module which is composed of a BCH (Bose-Chadhuri-Hocquenghem) cyclic encoder and control device was designed according as a four steps' generation process proposed in the bluetooth standard. The pseudo random sequence which solves syncronization problem saved a voluntary device Proposed the module was designed by VHDL. An simulation and test are inspected by Xilinx FPGA.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.17 no.3
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• pp.166-175
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• 2024

In this paper, the Window-Masking Method and HAT (Hardware Attached Top) CPU SoM (System on Module) are used to improve the performance and reduce the weight of the MANET (Mobile Ad-hoc Network) network synchronization system using time division redundancy. We propose converting it into a RISC-V based soft-core MCU and mounting it on an FPGA, a hardware accelerator. It was also verified through experiment. In terms of performance, by applying the proposed technique, the synchronization acquisition range is from -50dBm to +10dBm to -60dBm to +10dBm, the lowest input level for synchronization is increased by 20% from -50dBm to -60dBm, and the detection delay (Latency) is 220ns. Reduced by 43% to 125ns. In terms of weight reduction, computing resources (48%), size (33%), and weight (27%) were reduced by an average of 36% by replacing with soft-core MCU.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.180-187
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• 1996

This paper describes a post-layout simulation method using VHDL and C for verifying the architecture of antifuse-based FPGAs and the dedicated CAD system. An antifuse-based FPGA consists of programming circuitry including decoding logic, logic modules, segmented tracks, antifuses and I/O pads. The VHDL model which includes all these elements is used for logic verification and programming verification of the implemented circuit by reconstructing the logic circuit from the bit-stream generated from layout tool. The implemented circuit comprises of logic modules and routing networks. Since the routing delay of the complex networks is comparable to the delay of the logic module in the FPGA, the accurate post-layout simulation is essential to the FPGA system. In this paper, the C program calculates the delay of the routing netowrks using SPICE, elmore or horowitz delay models and the results feedback to the VHDL simulation. Critical path anc be found from this post-layout simulation results.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2003.06a
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• pp.300-303
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• 2003

In this paper, a baseband module of the spread spectrum system with FPGA is designed. A spread spectrum system spreads the signal bandwidth necessary for information transmission. We focused on the design of FEC decoder, especially the convolutional code fo constraint length K=3, rate R=l/2, is designed. For the VHDL design the Xilinx Foundation 3.1 is used. As results, a spread spectrum modem with convolutional coding is designed and we have plan to apply this modem to short distances wireless communication.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1655-1666
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• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.548-550
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• 2006

This paper deals with the implementation of a small humanoid robot controller on the basis of Real Time Operating System(RTOS) and the FPGA. This controller was adapted to the humanoid robot with 25 DOFs, which are 12 DOFs in each leg, 8 DOFs in each arm, 3 DOFs in waist, and 2 DOFs in head. The robot actuators were used DX-117 servo motors that have all of the controller components in one module in order to simplify the control structure. In addition, the main controller is FPGA of Virtex4-FX from Xilinx, and ported on VxWorks that is kind of RTOS. It is essential to install this RTOS on the complex control system and to do control activity at the multitasking environments. This paper suggested the method of distributing the computational load in the humanoid robot controller using the FPGA and RTOS concepts. All of the control process was verified through the real action of the humanoid.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.903-906
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• 2009

In this contribution, we designed a serial port interface (SPI) suitable for embedded systems, especially for Bluetooth baseband. Proposed architecture is compatible for the APB bus in AMBA bus architecture. The 8-bit design of the SPI module is in charge of transferring the data and the instructions between the external devices and the coprocessors. We adopted the cyclic redundancy check method for the error correction. Also, we provided the interface for multimedia cards. The designed SPI module was automatically synthesized, placed, and routed. Implementation was performed through the Altera FPGA and well operated at 25MHz clock frequency.

• Proceedings of the IEEK Conference
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• 2001.06d
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• pp.191-194
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• 2001

This paper presents a real-time implementation method of a laser pointer mouse system. This system consists of a camera, a FPGA circuits to track a laser footprint and RF module for communication between a laser pointer and the proposed system. We first simulate the system and realize the system by a FPGA circuit after implementing it by a VHDL.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.254-257
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• 2000

In this paper, we propose a structure of the modified AAL. The ATM adaptation layer(AAL) is described in HDL and implemented in FPGA, which plays a role in receiving of HDTV TS packets over ATM networks. Also We designed the PCI interface module which is used for monitoring and analyzing the HDTV TS packets. The designed FPGA chip operates at 20 MHz.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1304-1307
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• 2002

In this paper, we describe the structure and the test results of a Bluetooth baseband module we have developed. The module has a distributed buffer, i.e. FIFO, for data stream. Bus interface of the module is designed on the basis of interface of microprocessor widely used and the external interface is designed to consider chips connected directly. Since the module performs as many hardware efficient tasks as possible, processing load of microprocessor is very small. It can also be controlled either by software or by hardware for flexibility. The fully synthesizable baseband module was fabricated in a $0.25\mu\textrm{m}$ CMOS technology occupying $2.79\times2.8{\textrm{mm}^2}$ area. And an FPGA implementation of this module is tested for file and bit-stream transfers between PCs.