• Nuclear Engineering and Technology
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• v.50 no.5
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• pp.780-787
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• 2018

This article presents a security module based on a field programmable gate array (FPGA) to mitigate man-in-the-middle cyber attacks. Nowadays, the FPGA is considered to be the state of the art in nuclear power plants I&C systems due to its flexibility, reconfigurability, and maintainability of the FPGA technology; it also provides acceptable solutions for embedded computing applications that require cybersecurity. The proposed FPGA-based security module is developed to mitigate information-gathering attacks, which can be made by gaining physical access to the network, e.g., a man-in-the-middle attack, using a cryptographic process to ensure data confidentiality and integrity and prevent injecting malware or malicious data into the critical digital assets of a nuclear power plant data communication system. A model-based system engineering approach is applied. System requirements analysis and enhanced function flow block diagrams are created and simulated using CORE9 to compare the performance of the current and developed systems. Hardware description language code for encryption and serial communication is developed using Vivado Design Suite 2017.2 as a programming tool to run the system synthesis and implementation for performance simulation and design verification. Simple windows are developed using Java for physical testing and communication between a personal computer and the FPGA.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.4
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• pp.424-434
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• 2015

Adaptive beamforming algorithms have been widely used to remove interference and jamming in the phased array radar system. Advances in the field programmable gate array(FPGA) technology now make possible the real time processing of adaptive beamforming (ABF) algorithm. In this paper, the FPGA based real-time implementation method of adaptive beamforming system(beamformer) in the pre-processor module for active electronically scanned array(AESA) radar is proposed. A compact FPGA-based adaptive beamformer is developed using commercial off the shelf(COTS) FPGA board with communication via OpenVPX(Virtual Path Cross-connect) backplane. This beamformer comprises a number of high speed complex processing including QR decomposition & back substitution for matrix inversion and complex vector/matrix calculations. The implemented result shows that the adaptive beamforming patterns through FPGA correspond with results of simulation through Matlab. And also confirms the possibility of application in AESA radar due to the real time processing of ABF algorithm through FPGA.

• Journal of the Korea Society of Computer and Information
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• v.11 no.2 s.40
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• pp.159-167
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• 2006

Lipreading has been suggested as one of the methods to improve the performance of speech recognition in noisy environment. However, existing methods are developed and implemented only in software. This paper suggests a hardware design for real-time lipreading. For real-time processing and feasible implementation, we decompose the lipreading system into three parts; image acquisition module, feature vector extraction module, and recognition module. Image acquisition module capture input image by using CMOS image sensor. The feature vector extraction module extracts feature vector from the input image by using parallel block matching algorithm. The parallel block matching algorithm is coded and simulated for FPGA circuit. Recognition module uses HMM based recognition algorithm. The recognition algorithm is coded and simulated by using DSP chip. The simulation results show that a real-time lipreading system can be implemented in hardware.

• Journal of the Korean Society of Systems Engineering
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• v.14 no.2
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• pp.73-82
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• 2018

In this work, a hardware based cryptographic module for the cyber security of nuclear power plant is developed using a system engineering approach. Nuclear power plants are isolated from the Internet, but as shown in the case of Iran, Man-in-the-middle attacks (MITM) could be a threat to the safety of the nuclear facilities. This FPGA-based module does not have an operating system and it provides protection as a firewall and mitigates the cyber threats. The encryption equipment consists of an encryption module, a decryption module, and interfaces for communication between modules and systems. The Advanced Encryption Standard (AES)-128, which is formally approved as top level by U.S. National Security Agency for cryptographic algorithms, is adopted. The development of the cyber security module is implemented in two main phases: reverse engineering and re-engineering. In the reverse engineering phase, the cyber security plan and system requirements are analyzed, and the AES algorithm is decomposed into functional units. In the re-engineering phase, we model the logical architecture using Vitech CORE9 software and simulate it with the Enhanced Functional Flow Block Diagram (EFFBD), which confirms the performance improvements of the hardware-based cryptographic module as compared to software based cryptography. Following this, the Hardware description language (HDL) code is developed and tested to verify the integrity of the code. Then, the developed code is implemented on the FPGA and connected to the personal computer through Recommended Standard (RS)-232 communication to perform validation of the developed component. For the future work, the developed FPGA based encryption equipment will be verified and validated in its expected operating environment by connecting it to the Advanced power reactor (APR)-1400 simulator.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.6B
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• pp.630-640
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• 2009

The thesis suggests hand-held equipment to overhaul for mobile TFT LCD/OLED module of high-performance. The established module equipment to overhaul could distinguish outputting video data to module for distinguishing flicker, but it is impossible with low system. In this thesis, supporting system could check the various supplement functions from bringing equipment to overhaul without changing design of FPGA or H/W the module various size for equipment to overhaul for module of high-performance coincidently. The system includes hand-held equipment to overhaul, test software embedded and software a base personal computer and have designed to output, save, and certify all contents of module test of hand-held equipment to overhaul to interface universal serial bus. Setting up 9 items that represent for efficient verification of the proposed system have been possible confirmation with TFT LCD/OLED module of high-performance, establishment scan time, creation gamma, changing register, supporting interface, and multi inch modules.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.9
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• pp.124-129
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• 2009

Recently, PWM inverter is widely utilized for many industrial applications such as high performance drive and space vector pulse width modulation(SVPWM) inverter which has high voltage ratio and low harmonics compared to conventional PWM inverter. This paper presents the implementation on a field programmable gate array(FPGA) of a SVPWM module for a voltage source inverter. The SVPWM module consists of PWM generator, current and position sensor interface and dead time compensator. The implemented SVPWM module can be integrated with a digital signal processor(DSP) to provide a flexible and effective solution for high performance voltage source inverter and for the use of multi-motor control. The performance of SVPWM module is verified by simulation and several experimental results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.12A
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• pp.1261-1269
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• 2008

This paper presents an implementation of the Network Capable Application Processor (NCAP) and the Wireless Transducer Interface Module (WTIM) architectures based on the new IEEE P1451.5 standard. Proposed architecture is implemented using a computer for NCAP, an FPGA board, a sensor board and two radio modules, which communicate through the ZigBee wireless communication technology between the NCAP and the WTIM based on the IEEE 1451.0 and the IEEE 1451.5 interfaces. In this paper, two experiments has been done to verify operations of proposed architecture. From the experimental results, we verify that the proposed architecture performs the wireless sensor communication functions efficiently.

• Journal of Sensor Science and Technology
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• v.32 no.5
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• pp.320-327
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• 2023

In this study, an FPGA-based sealer inspection system was developed to inspect the sealer applied to install vehicle glass on a car body. The sealer is a liquid or paste-like material that promotes adhesion such as sealing and waterproofing for mounting and assembling vehicle parts to a car body. The system installed in the existing vehicle design parts line does not detect the sealer in the glass rotation section and takes a long time to process. This study developed a line laser camera sensor and an FPGA vision signal processing module to solve this problem. The line laser camera sensor was developed such that the resolution and speed of the camera for data acquisition could be modified according to the irradiation angle of the laser. Furthermore, it was developed considering the mountability of the entire system to prevent interference with the sealer ejection machine. In addition, a vision signal processing module was developed using the Zynq-7020 FPGA chip to improve the processing speed of the algorithm that converted the profile to the sealer shape image acquired from a 2D camera and calculated the width and height of the sealer using the converted profile. The performance of the developed sealer application inspection system was verified by establishing an experimental environment identical to that of an actual automobile production line. The experimental results confirmed the performance of the sealer application inspection at a level that satisfied the requirements of automotive field standards.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.2865-2867
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• 2000

In machine vision fields around FA, there have been demands for functions to capture high speed moving objects as blur-free images. By electronic shutters, progressive scan cameras can do it. This paper develops a module to connect a progressive scan camera, XC-55.

• Journal of the Institute of Convergence Signal Processing
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• v.14 no.4
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• pp.255-260
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• 2013

In this paper, we propose the effective bit expansion of FFT module for improving the accuracy of correlation result of the Daejeon correlator. The Daejeon correlator based on FPGA was implemented in order to fast data processing with the fixed-point of FFT operation. In correlation result, however, the phenomenon of phase concentration to 0 degree was appeared in lower frequency area of bandwidth due to lack of operational bit. This phenomenon has an affect on the accuracy of correlation result by introducing the effect of data loss because of excluding phase concentration during analysis of observed radio source. In order to improving the accuracy of correlation result we carried out the simulation by expanding bit-number than 16-bit operation of previous FFT module within given resource limits of FPGA. Through the simulation results, the effective bit number for FFT module within used FPGA resource limits is able to expand, and we confirmed that the operational 20-bit of FFT module is effective for improving accuracy of correlation result by comparing with experimental result.