• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.8
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• pp.578-584
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• 2004

The CSVM(Current Support Vector Machine) that is a digital architecture performing all phases of recognition process including kernel computing, learning, and recall of SVM(Support Vector Machine) on a chip is proposed. Concurrent operation by parallel architecture of elements generates high speed and throughput. The classification problems of bio data having high dimension are solved fast and easily using the CSVM. Quadratic programming in original SVM learning algorithm is not suitable for hardware implementation, due to its complexity and large memory consumption. Hardware-friendly SVM learning algorithms, kernel adatron and kernel perceptron, are embedded on a chip. Experiments on fixed-point algorithm having quantization error are performed and their results are compared with floating-point algorithm. CSVM implemented on FPGA chip generates fast and accurate results on high dimensional cancer data.

• Journal of Electrical Engineering and Technology
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• v.13 no.1
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• pp.192-200
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• 2018

In this study, improvements for error correction, speed, position, and rotation calculation algorithms have been proposed to be used in resolver to digital conversion (RDC) systems. The proposed open-loop system drives the resolver and uses the output signals of the resolver signal to estimate the real time position, the instant speed, and the rotation count with high resolution and accuracy even at high speeds and noise. The proposed solution implements strong features of both closed and open loop based systems while eliminating their weak points. The improvements proposed is resistant to noise owing to digital FIR filter and data averaging techniques. The implementation used for proof of concept is implemented on a hardware using an FPGA and configurable to be used by any resolver.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.7
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• pp.1478-1482
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• 2003

In this paper. Rijndael cipher algorithm is implemented by a hardware. It was selected as the AES(Advanced Encryption Standard) by NIST. It has structure that round operation divided into 2 subrounds and subrounds are pipelined to calculate efficiently. It takes 5 clocks for one-round. The AES-128 cipher algorithm is implemented for hardware by ALTERA FPGA, and, analyzed the performance. The AES-128 cipher algorithm has approximately 424 Mbps encryption rate for 166Mhz max clock frequency. In case of decryption, it has 363 Mbps decryption rate fu 142Mhz max clock frequency. In case of cipher core, it has 320Mbps encryptionㆍdecryption rate for 125Mhz max clock frequency.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.405-410
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• 2006

Future GNSS signal using BOC modulation brings the advantages of positioning accuracy and multipath rejection. However, the BOC signal has an ambiguous autocorrelation function that complicates the process of acquisition. Three techniques that solve the ambiguous problem are BPSK-like, Sub Carrier Phase Cancellation, and Bump Jumping. In this paper, these methods are implemented by means of a DSP/FPGA board. Moreover, an experiment is conducted to examine and compare the performance of these techniques.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.807-809
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• 2004

본 논문에서는 광 부호분할다중접속(OCDMA) 시스템 구현을 위해 각 가입자의 시간ㆍ파장영역의 2차원 부호할당 및 변경이 가능하고 다중 사용자의 암호화된 데이터의 동시 전송과 모든 수신 노드에서 복원이 가능한 OCDMA 시스템 구조를 제안하였다. 또한 기존의 이중 광 하드리미터를 제한증폭기와 AND 게이트를 사용하여 이중 전기 하드리미터를 구현하였다. 서로 다른 파장을 갖는 레이저 다이오드와 FPGA를 이용한 전기 상관기로서 시간과 파장영역의 2차원으로 부호 다중화된 동시 가입자 신호에서 특정 가입자의 신호를 복원하였고, 제한 검출기와 위치 검출기의 이중 전기 하드리미터를 이용하여 MAI로 인한 기존 OCDMA 시스템에서의 식별력 저하와 비트오류 문제를 해결하였다.

• The KIPS Transactions:PartC
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• v.19C no.1
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• pp.55-62
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• 2012

KT-64 is a 64-bit block cipher which use CSPNs suitable for the efficient FPGA implementation. In this paper, we propose a related-key amplified boomerang attack on the full-round KT-64. The attack on the full-round KT-64 requires $2^{45.5}$ related-key chosen plaintexts and $2^{65.17}$ KT-64 encryptions. This work is the first known cryptanalytic result on KT-64.

• Proceedings of the Korea Information Processing Society Conference
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• 2001.04a
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• pp.363-366
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• 2001

LILI-128 스트림 암호는 IMT-2000 무선단말간 데이터 암호화를 위하여 제안된 128-비트 크기의 스트림 암호방식이며, 클럭 조절형태의 채택에 따라 속도저하라는 구조적인 문제점을 안고 있다. 본 논문에서는 귀환/이동에 있어서 랜덤한 4개의 연결 경로를 갖는 4-비트병렬 $LFSR_{d}$를 제안함으로서 속도문제를 해결하였다. 그리고 ALTERA 사의 FPGA 소자(EPF10K20RC240-3)를 선정하여 그래픽/VHDL 하드웨어 구현 및 타이밍 시뮬레이션을 실시하였으며, 50MHz 시스템 클럭에서 안정적인 50Mbps (즉, 45 Mbps 수준인 T3급 이상, 설계회로의 최대 지연 시간이 20ns 이하인 조건) 출력 수열이 발생될 수 있음을 확인하였다. 마지막으로, FPGA/VHDL 설계회로를 Lucent ASIC 소자 ($LV160C,\;0.13{\mu}m\;CMOS\;&\;1.5v\;technology$)로 설계 변환 및 타이밍 시뮬레이션한 결과 최대 지연시간이 1.8ns 이하였고, 500 Mbps 이상의 고속화가 가능함을 확인하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.903-906
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• 2009

In this contribution, we designed a serial port interface (SPI) suitable for embedded systems, especially for Bluetooth baseband. Proposed architecture is compatible for the APB bus in AMBA bus architecture. The 8-bit design of the SPI module is in charge of transferring the data and the instructions between the external devices and the coprocessors. We adopted the cyclic redundancy check method for the error correction. Also, we provided the interface for multimedia cards. The designed SPI module was automatically synthesized, placed, and routed. Implementation was performed through the Altera FPGA and well operated at 25MHz clock frequency.

• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.2
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• pp.93-99
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• 2011

In this paper, an ATSC(Advanced Television Standard Committee)-M/H(Mobile/Handheld) multiplexer is designed and implemented using an embedded Linux based hardware platform. The ATSC-M/H multiplexer is composed of a CPU(Central Processor Unit), an FPGA(Field-Programmable Gate Array), ASI(Asynchronous Serial Interface)/SMPTE310(Society of Motion Picture and Television Engineers310) interface board, and a GPS(Global Position System) clock processing block. The main functions of the ATSC-M/H multiplexer executed in the CPU and FPGA are described. The operation of the ATSC-M/H multiplexer is verified by processing its broadcast signal on a commercial receiver analyzer.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.890-893
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• 2014

In this paper, we present a signal processing algorithm for a marine radar system, in which the evaluation of probability of collision as well as target detection and tracking are performed. Moreover, the digital signal processor that implements the algorithm is proposed. As simulation environment, a mechanically scanning antenna utilizing FMCW signal is used, conducting the beamforming operation with 1 degrees intervals. Test board consists of DSP chips and FPGA, which enable the implemented system to operate in real-time.