• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.2
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• pp.135-140
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• 2014

In this paper, we describe the contents of noise characteristic enhancement using digital filtering to the motion vector in the pattern noise of optical mouse. The designed circuit is implemented to enhance the smoothing and trembling with filtering and averaging of x, y motion vector before PS2 or USB output. The function is verified by using FPGA and the performance is measured by the fabricated chip using $0.35{\mu}m$ standard CMOS process. The system clock is 6MHz and the motion vector has the range of +6 to -6 per 1/1700sec. It is tested using the Cartesian robot to measure the noise characteristic enhancement.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.51 no.8
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• pp.360-367
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• 2002

In this paper, genetic algorithm based adaptive image enhancement filtering scheme is proposed and Implemented on FPGA board. Conventional filtering methods require a priori noise information for image enhancement. In general, if a priori information of noise is not available, heuristic intuition or time consuming recursive calculations are required for image enhancement. Contrary to the conventional filtering methods, the proposed filter system can find optimal combination of filters as well as their sequent order and parameter values adaptively to unknown noise types using structured genetic algorithms. The proposed image enhancement filter system is mainly composed of two blocks. The first block consists of genetic algorithm part and fitness evaluation part. And the second block consists of four types of filters. The first block (genetic algorithms and fitness evaluation blocks) is implemented on host computer using C code, and the second block is implemented on re-configurabe FPGA board. For gray scale control, smoothing and deblurring, four types of filters(median filter, histogram equalization filter, local enhancement filter, and 2D FIR filter) are implemented on FPGA. For evaluation, three types of noises are used and experimental results show that the Proposed scheme can generate optimal set of filters adaptively without a pioi noise information.

• Journal of IKEEE
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• v.19 no.3
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• pp.335-341
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• 2015

Recently a demand for high precision absolute position transducer is increasing in order to control thickness in steel industry. LVDT (linear variable differential transformer) is widely used to measure the absolute position in the linearly moving cylinder under poor factory environment. In this paper we implement the three phase LVDT with a high resolution of one micron and L/D (LVDT to digital) converter. First we designed U, V, and W three phase signaling using FPGA. Second a pulse output algorithm is designed for position information with A and B phase waveforms. Finally the performance is compared with previous sensors. Experiments show that the linearity deviation error is 0.009788 [mm] and the average sinusoidal THD is 0.0751%, which means 2.2% and 33% more improved result than the previous sensors respectively.

• The Journal of the Acoustical Society of Korea
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• v.19 no.3
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• pp.11-19
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• 2000

This research deals with the implementation procedures of a chorus processing DSP for karaoke system. It is necessary to compress the chorus data to store as many choruses as we can. We apply MPEG-1 audio algorithm to compress the chorus data. And the chorus system must be accompanied with the karaoke that can change the key and the tempo. So the chorus DSP must be able to change the key and tempo of the chorus data. We apply SOLA (Synchronized Overlap and Add) to do it. We designed the chorus DSP that can compress the chorus, change the key and tempo. And we verified the chorus DSP logic using FPGA. The used FPGA are two FLEX10K100s made by ALTERA. Finally we make the ASIC chip of chorus DSP and verify its operation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.196-198
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• 2003

In this paper, Rijndal cipher algorithm is implemented by a hardware. It is selected as the AES(Advanced Encryption Standard) by NIST. The processor has structure that round operation divided into 2 subrounds and subrounds are pipelined to calculate efficiently. It takes 5 clocks for one-round. The AES-128 cipher algorithm is implemented for hardware by ALTERA FPGA, and then, analyzed the performance. The AES-128 cipher algorithm has approximately 424 Mbps encryption rate for 166Mhz max clerk frequency. In case of decryption, it has 363 Mbps decryption rate for 142Mhz max clock frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.8
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• pp.1777-1781
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• 2011

Tosin backplane system design of this study (Backplane) from the HSTL (High-Speed Transceiver Logic) characteristics of the transmit and receive data using the HSPICE simulations and the actual implementation on the FPGA Data transmission characteristics were described by comparing the simulation results. Simulation and measurement criteria for point to point data transmission characteristics of wire length possible to send and receive data about the speed limits were reviewed. Measured point to point connection to send and receive signals at terminal velocity, the factors that affect the electrical noise around the wire length and showed a very important role.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.05a
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• pp.1071-1074
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• 2005

The ECC(Elliptic Curve Cryptogrphics), one of the representative Public Key encryption algorithms, is used in Digital Signature, Encryption, Decryption and Key exchange etc. The key operation of an Elliptic curve cryptosystem is a scalar multiplication, hence the design of a scalar multiplier is the core of this paper. Although an Integer operation is computed in infinite field, the scalar multiplication is computed in finite field through adding points on Elliptic curve. In this paper, we implemented scalar multiplier in Elliptic curve based on the finite field $GF(2^{163})$. And we verified it on the Embedded digital system using Xilinx FPGA connected to an EISC MCU(Agent 2000). If my design is made as a chip, the performance of scalar multiplier applied to Samsung $0.35\;{\mu}m$ Phantom Cell Library is expected to process at the rate of 8kbps and satisfy to make up an encryption processor for the Embedded digital information home system.

• The Journal of the Korea Contents Association
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• v.13 no.4
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• pp.44-52
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• 2013

The SIFT algorithm is being actively researched for various image processing applications including video surveillance and autonomous vehicle navigation. The computation of sin/cos function is the most cost part needed in whole computational complexity and time for SIFT descriptor. In this paper, we implement a hardware to sin/cos function of descriptor on sift feature detection algorithm. The proposed Sin/Cosine processor is coded in Verilog and synthesized and simulated using Xilinx ISE 9.2i. The processor is mapped onto the device Spartan 2E (XC2S200E-PQ208-6). It consumes 149 slices, 233 LUTs and attains a maximum operation frequency of 60.01 MHz. As compared with the software realization, our FPGA circuit can achieve the speed improvement by 40 times in average.

• Journal of the Korean Institute of Intelligent Systems
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• v.11 no.8
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• pp.764-770
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• 2001

In this paper, we propose a novel PCI bus based parallel fuzzy inference system for transferring and inferencing the large volumes of fuzzy data in high speed. For this, the PCI 9050 interface chip is used to connect a local bus design as a PCI target core using FPGA to the PCI bus. We design and implement the PCI target core by using VHDL to be processed in parallel by considering the points of parallelyzing each element of the membership functions and each block of the condition and/or consequent parts. The proposed system can be used in a system requiring a rapid inference time in a real-time system or pattern recognition on the large volume of satellite images that have many inference variables in the condition and consequent parts.

• Journal of the Korea Society of Computer and Information
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• v.21 no.11
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• pp.31-38
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• 2016

In this paper, we propose multi-scale infrared target detection algorithm with varied filter size using integral image. Filter based target detection is widely used for small target detection, but it doesn't suit for large target detection depending on the filter size. When there are multi-scale targets on the sky background, detection filter with small filter size can not detect the whole shape of the large targe. In contrast, detection filter with large filter size doesn't suit for small target detection, but also it requires a large amount of processing time. The proposed algorithm integrates the filtering results of varied filter size for the detection of small and large targets. The proposed algorithm has good performance for both small and large target detection. Furthermore, the proposed algorithm requires a less processing time, since it use the integral image to make the mean images with different filter sizes for subtraction between the original image and the respective mean image. In addition, we propose the implementation of real-time embedded system using FPGA.