• Title/Summary/Keyword: FPGA 데이터수집보드

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Implementation of High Speed Image Data Transfer using XDMA

  • Gwon, Hyeok-Jin;Choi, Doo-Hyun
    • Journal of the Korea Society of Computer and Information
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    • v.25 no.7
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    • pp.1-8
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    • 2020
  • In this paper, we present an implementation of high speed image data transfer using XDMA for a video signal generation / acquisition device developed as a military test equipment. The technology proposed in this study obtains efficiency by replacing the method of copying data using the system buffer in the kernel area with the transmission and reception through the DMA engine in the FPGA. For this study, the device was developed as a PXIe platform in consideration of life cycle, and performance was maximized by using a low-cost FPGA considering mass productivity. The video I/O board implemented in this paper was tested by changing the AXI interface clock frequency and link speed through the existing memory copy method. In addition, the board was constructed using the DMA engine of the FPGA, and as a result, it was confirmed that the transfer speed was increased from 5~8Hz to 140Hz. The proposed method will contribute to strengthening defense capability by reducing the cost of device development using the PXIe platform and increasing the technology level.

A Study on the Fuel Injection System Simulating a Vehicle Driven with FTP-75 Mode for Cold Transition Period (FTP-75 냉간 주행 모드로 운전하는 차량의 연료분사 모사시스템에 관한 연구)

  • Oh, Dae-San;Lee, Choong-Hoon
    • Journal of ILASS-Korea
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    • v.16 no.2
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    • pp.76-81
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    • 2011
  • A fuel injection system which is operated with a real vehicle driving simulation was developed as an alternative to a vehicle test for the fuel injectors. The sensor signals that are supplied to the ECU were measured and recorded as a data file for a vehicle driven in FTP-75 mode in a chassis dynamometer. The imperative sensor signals of the throttle position, vehicle speed, engine speed, crank position, cam position, intake air flow, and cooling water and intake air temperature were reconstructed using FPGA DAQ boards and a PXI computer. The scanning results showed good agreement with the input signals that were reconstructed. The ECU HILS system operated successfully to drive six fuel injectors, which injected fuel in the same pattern as if they were mounted in the vehicle driven in FTP-75 mode. Also, the fuel injection system developed in this research shows the possibility of application in evaluating the characteristics of fuel injection rate for injectors according to properties of injected fuel with the real driving mode of vehicles.

Application Scenario of Integrated Development Environment for Autonomous IoT Applications based on Neuromorphic Architecture (뉴로모픽 아키텍처 기반 자율형 IoT 응용 통합개발환경 응용 시나리오)

  • Park, Jisu;Kim, Seoyeon;Kim, Hoinam;Jeong, Jaehyeok;Kim, Kyeongsoo;Jung, Jinman;Yun, Young-Sun
    • Smart Media Journal
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    • v.11 no.2
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    • pp.63-69
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    • 2022
  • As the use of various IoT devices increases, the importance of IoT platforms is also rising. Recently, artificial intelligence technology is being combined with IoT devices, and research applying a neuromorphic architecture to IoT devices with low power is also increasing. In this paper, an application scenario is proposed based on NA-IDE (Neuromorphic Architecture-based autonomous IoT application integrated development environment) with IoT devices and FPGA devices in a GUI format. The proposed scenario connects a camera module to an IoT device, collects MNIST dataset images online, recognizes the collected images through a neuromorphic board, and displays the recognition results through a device module connected to other IoT devices. If the neuromorphic architecture is applied to many IoT devices and used for various application services, the autonomous IoT application integrated development environment based on the neuromorphic architecture is expected to emerge as a core technology leading the 4th industrial revolution.

Tag-free Indoor Positioning System Using Wireless Infrared and Ultrasonic Sensor Grid (적외선 및 초음파센서 그리드를 활용한 태그가 없는 실내 위치식별 시스템)

  • Roh, Chanhwi;Kim, Yongseok;Shin, Changsik;Baek, Donkyu
    • Journal of Korea Society of Industrial Information Systems
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    • v.27 no.1
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    • pp.27-35
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    • 2022
  • In the most IPS (Indoor Positioning System), it is available to specify the user's movement by sending a specific signal from a tag such as a beacon to multiple receivers. This method is very efficiently used in places where the number of people is limited. On the other hand, in large commercial facilities, it is nearly difficult to apply the existing IPS method because it is necessary to attach a tag to each customer. In this paper, we propose a system that uses an external sensor grid to identify people's movement without using tags. Each sensor node uses both an ultrasonic sensor and an infrared sensor to monitor people's movements and sends collected data to the main server through wireless transmission for easy system maintenance. The operation was verified using the FPGA board, and we designed a VLSI circuit in 180nm process.

The Hardware Design and Implementation of a New Ultra Lightweight Block Cipher (새로운 초경량 블록 암호의 하드웨어 설계 및 구현)

  • Gookyi Dennis, A.N.;Park, Seungyong;Ryoo, Kwangki
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.10
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    • pp.103-108
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    • 2016
  • With the growing trend of pervasive computing, (the idea that technology is moving beyond personal computers to everyday devices) there is a growing demand for lightweight ciphers to safeguard data in a network that is always available. For all block cipher applications, the AES is the preferred choice. However, devices used in pervasive computing have extremely constraint environment and as such the AES will not be suitable. In this paper we design and implement a new lightweight compact block cipher that takes advantage of both S-P network and the Feistel structure. The cipher uses the S-box of PRESENT algorithm and a key dependent one stage omega permutation network is used as the cipher's P-box. The cipher is implemented on iNEXT-V6 board equipped with virtex-6 FPGA. The design synthesized to 196 slices at 337 MHz maximum clock frequency.