• Journal of Korea Society of Industrial Information Systems
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• v.18 no.2
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• pp.1-12
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• 2013

Information Security System is implemented in software, hardware and FPGA device. Implementation of S/W provides high flexibility about various information security algorithm, but it has very vulnerable aspect of speed, power, safety, and performing ASIC is really excellent aspect of speed and power but don't support various security platform because of feature's realization. To improve conflict of these problems, implementation of recent FPGA device is really performed. The goal of this thesis is to design and develop a FPGA hardware accelerator for information security system. It performs as AES, SHA-256 and ECC and is controlled by the Integrated Interface. Furthermore, since the proposed Security Information System can satisfy various requirements and some constraints, it can be applied to numerous information security applications from low-cost applications and high-speed communication systems.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2022.11a
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• pp.349-350
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• 2022

Recently, AI (Artificial Intelligence) has been applied to various technologies such as automatic driving, robot and smart communication. Currently, AI system is developed by software-based method using tensor flow, and GPU (Graphic Processing Unit) is employed for processing unit. In this work, we developed an FPGA-based (Field Programmable Gate Array) AI system , and report on image recognition system to realize the AI system.

• The KIPS Transactions:PartC
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• v.8C no.3
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• pp.277-286
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• 2001

본 논문에서는 미국 국립표준기술연구소 차세대 표준 암호 알고리듬으로 선정한 Rijndael 암호 알고리듬과 안정성과 성능에서 인정을 받은 Twofish 암호 알고리듬을 ALTERA FPGA를 사용하여 하드웨어로 구현한다. 두가지 알고리듬에 대해 키스케쥴링과 인터페이스를 하드웨어에 포함시켜 구현한다. 알고리듬의 효율적인 동작을 위해 키스케쥴링을 포함하면서도 구현된 회로의 크기가 크게 증가하지 않으며, 데이터의 암호/복호화 처리 속도가 향상됨을 알 수 있다. 주어진 128-비트 대칭키에 대하여, 구현된 Rijndael 암호 알고리듬은 11개의 클럭 만에 키스케쥴링을 완료하며, 구현된 Twofish 암호 알고리듬은 21개의 클럭 만에 키스케쥴링을 완료한다. 128-비트 입력 데이터가 주어졌을 때, Rijndael의 경우, 10개의 클럭 만에 주어진 데이터의 암호/복호화를 수행하고, Twofish는 16개의 클럭 만에 암호/복호화를 수행한다. 또한, Rijndael은 336.8Mbps의 데이터 처리속도를 보이고, Twofish는 121.2Mbps의 성능을 보임을 알 수 있다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.4
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• pp.424-434
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• 2015

Adaptive beamforming algorithms have been widely used to remove interference and jamming in the phased array radar system. Advances in the field programmable gate array(FPGA) technology now make possible the real time processing of adaptive beamforming (ABF) algorithm. In this paper, the FPGA based real-time implementation method of adaptive beamforming system(beamformer) in the pre-processor module for active electronically scanned array(AESA) radar is proposed. A compact FPGA-based adaptive beamformer is developed using commercial off the shelf(COTS) FPGA board with communication via OpenVPX(Virtual Path Cross-connect) backplane. This beamformer comprises a number of high speed complex processing including QR decomposition & back substitution for matrix inversion and complex vector/matrix calculations. The implemented result shows that the adaptive beamforming patterns through FPGA correspond with results of simulation through Matlab. And also confirms the possibility of application in AESA radar due to the real time processing of ABF algorithm through FPGA.

• Proceedings of the Acoustical Society of Korea Conference
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• 1998.06c
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• pp.347-350
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• 1998

최근 개인 휴대통신과 컴퓨터 기술의 발달로 유용한 데이터의 질적.양적 향상을 가져왔다. 이로 인해 저장중이거나 선로상에서의 전송중인 정보의 보호문제가 중요시되고 있다. 이러한 정보보호 문제가 중요시됨에 따라 정보보호를 위한 직접적인 암호화 방법중의 하나인 IDEA(International Data Encryption Algorithm)의 구현을 제안하고자 한다. IDEA는 블록 암호화 방식의 하나로서 64비트 데이터를 암호화하기 위해 128비트의 키를 사용한다. 본 논문에서 암호알고리즘 구현을 위하여 하드웨어 설계언어인 VHDL을 사용하였고, V-System을 이용하여 Simulation을 수행하였다. Coding된 알고리즘은 Synopsy를 사용하여 자동합성하였고, Xilinx사의 FPGA-4025를 Target으로 구현하였다.

• Journal of Korea Multimedia Society
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• v.15 no.7
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• pp.920-930
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• 2012

In this paper, we designed and built a wired temperature controller system which is based on ASIC for a wireless temperature controller system based on FPGA. FPGA devices and wireless controller systems are growing quickly especially for industrial systems for sensing temperature and humidity. FPGA can set up a desired system and a CPU, and directly set up or change a peripheral device based on an IP quickly for an affordable price. This wireless system is easy to install in the field where there are lots of changes and the system is complex. It also has advantages for maintenance. In this study, we are using a 32 bit RISC CPU based on MicroBlaze, with a touch interface, peripheral device, and porting the embedded Linux. Also, we added wireless communication using ZigBee. With this system we provide remote monitoring and control through the web by adding a web server. Compared to the original system, we say not only a performance improvement, but also more efficient development and cheaper costs. In this study, we focused especially on building a better development environment and a more effective user interface.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.3
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• pp.512-517
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• 2006

In this study, we designed a digital fuzzy logic controller based on FPGA for MPPT of the solar power generation system. A fuzzy algorithm to control the power tracking function of a boost converter has been built into the FPGA, and applied to the small scaled solar power generation system. The embodied controller showed a stable operation characteristic with the small output voltage ripple for the intensity change of solar radiation. This result proves that the implementation of the power tracking controller using FPGA is an effective way compared to the existing one using microprocessors.

• Journal of KIISE:Computing Practices and Letters
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• v.7 no.4
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• pp.372-381
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• 2001

In this paper SEED, the Korea Standard 128-bit block cipher algorithm is implemented with VHDL and mapped into one FPGA. SEED consists of round key generation block, F function block, G function block, round processing block, control block and I/O block. The designed SEED is realized in an FPGA but we design it technology-independently so that ASIC or core-based implementation is possible. SEED requires many hardware resources which may be impossible to realize in one FPGA. So it is necessary to minimize hardware resources. In this paper only one G function is implemented and is used for both the F function block and the round key block. That is, by using one G function sequentially, we can realize all the SEED components in one FPGA. The used cell rate after synthesis is 80% in Altem FLEXI0KlOO. The resulted design has 28Mhz clock speed and 14.9Mbps performance. The SEED hardware is technology-independent and no other external component is needed. Thus, it can be applied to other SEED implementations and cipher systems which use SEED.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.670-673
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• 2008

Optimized algorithms and numerical expressions which had been verified through C program simulation, should be analyzed again with HDL (hardware description language) such as Verilog, so that the verified ones could be modified to be applied directly to hardware implementation. The reason is that the characteristics of C programming language design is intrinsically different from the hardware design structure. The hardware IP verified doubly in view of hardware structure together with algorithmic verification, was implemented on the Altera Excalibur FPGA device equipped with ARM9 microprocessor core, to a real chip prototype, using Altera embedded system development tool kit. The implemented finite field calculation IPs can be used as library modules as Elliptic Curve Cryptography finite field operations which has more than 193 bit key length.

• Proceedings of the Korea Information Processing Society Conference
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• 2023.05a
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• pp.23-25
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• 2023

본 논문에서는 FPGA 를 활용하여 radix-2 Fast Fourier Transform(FFT) 알고리즘을 빠르고 효율적으로 구현하는 연구에 대해 기술한다. 본 논문에서 zybo z7-20 FPGA 를 사용하여 Processing System(PS)에서만 동작하는 구현과 Programmable Logic(PL)에서 동작하며 파이프라인과 병렬처리를 사용한 FFT 구현 결과를 비교한다. 또한 유사한 논문과의 결과 비교를 통해 본 구현 방법의 연산 시간 및 리소스 사용의 효율성을 분석한다.