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http://dx.doi.org/10.9723/jksiis.2013.18.2.001

Design of FPGA Hardware Accelerator for Information Security System  

Cha, Jeong Woo (대구대학교 대학원 컴퓨터정보공학과)
Kim, Chang Hoon (대구대학교 대학원 컴퓨터정보공학과)
Publication Information
Journal of Korea Society of Industrial Information Systems / v.18, no.2, 2013 , pp. 1-12 More about this Journal
Abstract
Information Security System is implemented in software, hardware and FPGA device. Implementation of S/W provides high flexibility about various information security algorithm, but it has very vulnerable aspect of speed, power, safety, and performing ASIC is really excellent aspect of speed and power but don't support various security platform because of feature's realization. To improve conflict of these problems, implementation of recent FPGA device is really performed. The goal of this thesis is to design and develop a FPGA hardware accelerator for information security system. It performs as AES, SHA-256 and ECC and is controlled by the Integrated Interface. Furthermore, since the proposed Security Information System can satisfy various requirements and some constraints, it can be applied to numerous information security applications from low-cost applications and high-speed communication systems.
Keywords
Security Information; FPGA; AES; SHA-256; ECC;
Citations & Related Records
Times Cited By KSCI : 3  (Citation Analysis)
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