• Journal of Broadcast Engineering
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• v.18 no.2
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• pp.178-184
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• 2013

In this paper, we propose an efficient parallelization technique of PU-level motion estimation (ME) in the next generation video coding standard, high efficiency video coding (HEVC) to reduce the time complexity of video encoding. It is difficult to encode video in real-time because ME has significant complexity (i.e., 80 percent at the encoder). In order to solve this problem, various techniques have been studied, and among them is the parallelization, which is carefully concerned in algorithm-level ME design. In this regard, merge estimation method using merge estimation region (MER) that enables ME to be designed in parallel has been proposed; but, parallel ME based on MER has still unconsidered problems to be implemented ideally in HEVC test model (HM). Therefore, we propose two strategies to implement stable parallel ME using MER in HM. Through experimental results, the excellence of our proposed methods is shown; the encoding time using the proposed method is reduced by 25.64 percent on average of that of HM which uses sequential ME.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.12
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• pp.867-879
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• 2006

This paper concerns fast and time accurate HW/SW cosimulation for MPSoC(Multi-Processor System-on-chip) architecture where multiple software and/or hardware components exist. It is becoming more and more common to use MPSoC architecture to design complex embedded systems. In cosimulation of such architecture, as the number of the component simulators participating in the cosimulation increases, the time synchronization overhead among simulators increases, thereby resulting in low overall cosimulation performance. Although SystemC cosimulation frameworks show high cosimulation performance, it is in inverse proportion to the number of simulators. In this paper, we extend the novel technique, called virtual synchronization, which boosts cosimulation speed by reducing time synchronization overhead: (1) SystemC simulation is supported seamlessly in the virtual synchronization framework without requiring the modification on SystemC kernel (2) Parallel execution of component simulators with virtual synchronization is supported. We compared the performance and accuracy of the proposed parallel SystemC cosimulation framework with MaxSim, a well-known commercial SystemC cosimulation framework, and the proposed one showed 11 times faster performance for H.263 decoder example, while the accuracy was maintained below 5%.

• KIPS Transactions on Software and Data Engineering
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• v.3 no.10
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• pp.397-406
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• 2014

In order to answer the questions successfully on behalf of the human in DeepQA environments such as Jeopardy! of the American quiz show, the computer is required to have the capability of fast temporal and spatial reasoning on a large-scale commonsense knowledge base. In this paper, we present a scalable spatial reasoning algorithm for deriving efficiently new directional and topological relations using the MapReduce framework, one of well-known parallel distributed computing environments. The proposed reasoning algorithm assumes as input a large-scale spatial knowledge base including CSD-9 directional relations and RCC-8 topological relations. To infer new directional and topological relations from the given spatial knowledge base, it performs the cross-consistency checks as well as the path-consistency checks on the knowledge base. To maximize the parallelism of reasoning computations according to the principle of the MapReduce framework, we design the algorithm to partition effectively the large knowledge base into smaller ones and distribute them over multiple computing nodes at the map phase. And then, at the reduce phase, the algorithm infers the new knowledge from distributed spatial knowledge bases. Through experiments performed on the sample knowledge base with the MapReduce-based implementation of our algorithm, we proved the high performance of our large-scale spatial reasoner.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.34 no.1
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• pp.53-62
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• 2016

In recent years, UAV Photogrammetry based on an ultra-light UAS(Unmanned Aerial System) installed with a low-cost compact navigation device and a camera has attracted great attention through fast and accurate acquirement of geo-spatial data. In particular, UAV Photogrammetry do gradually replace the traditional aerial photogrammetry because it is able to produce DEMs(Digital Elevation Models) and Orthophotos rapidly owing to large amounts of high resolution image collection by a low-cost camera and image processing software combined with computer vision technique. With these advantages, UAV-Photogrammetry has therefore been applying to a large scale mapping and cadastral surveying that require accurate position information. This paper presents experimental results of an accuracy performance test with images of 4cm GSD from a fixed wing UAS to demarcate parcel boundaries in agricultural area. Consequently, the accuracy of boundary point extracted from UAS orthoimage has shown less than 8cm compared with that of terrestrial cadastral surveying. This means that UAV images satisfy the tolerance limit of distance error in cadastral surveying for the scale of 1: 500. And also, the area deviation is negligible small, about 0.2%(3.3m²), against true area of 1,969m² by cadastral surveying. UAV-Photogrammetry is therefore as a promising technology to demarcate parcel boundaries.

• Journal of the Korea Society of Computer and Information
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• v.20 no.5
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• pp.1-12
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• 2015

NAND flash memory has being used for storage systems widely, because it has good features which are low-price, low-power and fast access speed. However, NAND flash memory has an in-place update problem, and therefore it needs FTL(flash translation layer) to run for applications based on hard disk storage. The FTL includes complex functions, such as address mapping, garbage collection, wear leveling and so on. Futhermore, implementation of the FTL on low-power embedded systems is difficult due to its memory requirements and operation overhead. Accordingly, many index data structures for NAND flash memory have being studied for the embedded systems. Overall performances of the index data structures are enhanced by a decreasing of page write counts, whereas it has increased page read counts, as a side effect. Therefore, we propose an index management method using a page mapping log table in $B^+$-Tree based on NAND flash memory to decrease page write counts and not to increase page read counts. The page mapping log table registers page address information of changed index node and then it is exploited when retrieving records. In our experiment, the proposed method reduces the page read counts about 61% at maximum and the page write counts about 31% at maximum, compared to the related studies of index data structures.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.49 no.4
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• pp.10-16
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• 2012

For high speed visual inspection in semiconductor industries, it is essential to acquire two-dimensional images on regions of interests with a large field of view (FOV) and a high resolution simultaneously. In this paper, an imaging system is newly proposed to achieve high quality image in terms of precision and FOV, which is composed of single lens, a beam splitter, two camera sensors, and stereo image grabbing board. For simultaneously acquired object images from two camera sensors, Zhang's camera calibration method is applied to calibrate each camera first of all. Secondly, to find a mathematical mapping function between two images acquired from different view cameras, the matching matrix from multiview camera geometry is calculated based on their image homography. Through the image homography, two images are finally registered to secure a large inspection FOV. Here the inspection system of using multiple images from multiple cameras need very fast processing unit for real-time image matching. For this purpose, parallel processing hardware and software are utilized, such as Compute Unified Device Architecture (CUDA). As a result, we can obtain a matched image from two separated images in real-time. Finally, the acquired homography is evaluated in term of accuracy through a series of experiments, and the obtained results shows the effectiveness of the proposed system and method.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.27 no.6
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• pp.733-739
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• 2009

Recently it is being increased rapidly to install magnetic marker and RFID tag on the underground utility lines before backfilling to ensure effective it's management. However, due to changes an attitude and damages of sensors. By pressure and vibration during soil compacting, detecting rate is significantly reduced as well as it allows to use only one line of various pipes since it has an unique frequency. Also it is required too long time to reach to target point with an non-accurate navigational GPS receiver and hard to update existing data base with a manual input of new data in the field. To improve these problems, the researcher developed the field management system that apply with ball typed self-levelling marker which is free from the changes of attitude for sensors during compaction as well as has various radio frequency applicable to many kind of pipes and ensure fast positioning to target point using an incorporated system with PDA based DGPS receiver which allows loading a field GIS software and RFID detector. Further, it provides with viewing all of RFID data on the DGPS receiver screen directly and also input new data to existing data base in the field automatically.

• Journal of KIISE:Software and Applications
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• v.31 no.4
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• pp.467-477
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• 2004

While recommender systems were used by a few E-commerce sites former days, they are now becoming serious business tools that are re-shaping the world of I-commerce. And collaborative filtering has been a very successful recommendation technique in both research and practice. But there are two problems in personalized recommender systems, it is First-Rating problem and Sparsity problem. In this paper, we solve these problems using the associative relation clustering and “Lift” of association rules. We produce “Lift” between items using user's rating data. And we apply Threshold by -cut to the association between items. To make an efficiency of associative relation cluster higher, we use not only the existing Hypergraph Clique Clustering algorithm but also the suggested Split Cluster method. If the cluster is completed, we calculate a similarity iten in each inner cluster. And the index is saved in the database for the fast access. We apply the creating index to predict the preference for new items. To estimate the Performance, the suggested method is compared with existing collaborative filtering techniques. As a result, the proposed method is efficient for improving the accuracy of prediction through solving problems of existing collaborative filtering techniques.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2005.10a
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• pp.103-109
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• 2005

At the adjacent sea area of Busan Central Wharf, a variety of vessels, such as middle-large passenger ships, small fast sailing ships, container ships, cargo ships and working ships as well as small miscellaneous vessels are freely sailing comparatively without special steering and sailing Rules and marine traffic control because exclusive wharfs in accord with their purpose and use have been arranged in each wharf. In this research, we analyzed traffic stream and navigational characteristics of main traffic route based on statistics and distribution of tracks by ship's type and tonnage of the passing vessels after conducting marine traffic survey twice using exclusive software by targeting the sea area during the period of time. We examined the traffic safety of the passing vessels by classifying the sea area by each function based on the analysis about this traffic situation, and analyzing the effect by designating 'Buknea passage'. We also studied the plan for the effective rearrangement of Central Wharf considering basically the traffic safety oif arrival and departure in a point if view of navigators.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2B
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• pp.1-10
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• 2005

TCP/IP protocols have been implemented in software program running on CPU in end systems. As the increased demand of fast protocol processing, it is required to implement the protocols in hardware, and Host Interface is responsible for communication between external CPU and the hardware blocks of TCP/IP implementation. The Host Interface follows AMBA AHB specification for the communication with external world. For control flow, the Host Interface behaves as a slave of AMBA AHB. Using internal Command/status Registers, the Host Interface receives commands from CPU and transfers hardware status and header information to CPU. On the other hand, the Host Interface behaves as a master for data flow. Data flow has two directions, Receive Flow and Transmit Flow. In Receive Flow, using internal RxFIFO, the Host Interface reads data from UDP FIFO or TCP buffer and transfers data to external RAM for CPU to read. For Transmit Flow, the Host Interface reads data from external RAM and transfers data to UDP buffer or TCP buffer through internal TxFIFO. TCP/IP hardware blocks generate packets using the data and transmit. Buffer Descriptor is one of the Command/Status Registers, and the information stored in Buffer Descriptor is used for external RAM access. Several testcases are designed to verify TCP/IP functions. The Host Interface is synthesized using the 0.18 micron technology, and it results in 173 K gates including the Command/status Registers and internal FIFOs.