• Title/Summary/Keyword: Extended Min-sum Algorithm

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Selection-based Low-cost Check Node Operation for Extended Min-Sum Algorithm

  • Park, Kyeongbin;Chung, Ki-Seok
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.15 no.2
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    • pp.485-499
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    • 2021
  • Although non-binary low-density parity-check (NB-LDPC) codes have better error-correction capability than that of binary LDPC codes, their decoding complexity is significantly higher. Therefore, it is crucial to reduce the decoding complexity of NB-LDPC while maintaining their error-correction capability to adopt them for various applications. The extended min-sum (EMS) algorithm is widely used for decoding NB-LDPC codes, and it reduces the complexity of check node (CN) operations via message truncation. Herein, we propose a low-cost CN processing method to reduce the complexity of CN operations, which take most of the decoding time. Unlike existing studies on low complexity CN operations, the proposed method employs quick selection algorithm, thereby reducing the hardware complexity and CN operation time. The experimental results show that the proposed selection-based CN operation is more than three times faster and achieves better error-correction performance than the conventional EMS algorithm.

Fully-Parallel Architecture for 1.4 Gbps Non-Binary LDPC Codes Decoder (1.4 Gbps 비이진 LDPC 코드 복호기를 위한 Fully-Parallel 아키텍처)

  • Choi, Injun;Kim, Ji-Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.4
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    • pp.48-58
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    • 2016
  • This paper presents the high-throughput fully-parallel architecture for GF(64) (160,80) regular (2,4) non-binary LDPC (NB-LDPC) codes decoder based on the extended min sum algorithm. We exploit the NB-LDPC code that features a very low check node and variable node degree to reduce the complexity of decoder. This paper designs the fully-parallel architecture and allows the interleaving check node and variable node to increase the throughput of the decoder. We further improve the throughput by the proposed early sorting to reduce the latency of the check node operation. The proposed decoder has the latency of 37 cycles in the one decoding iteration and achieves a high throughput of 1402Mbps at 625MHz.

MAX-MIN Flow Control Supporting Dynamic Bandwidth Request of Sessions (세션의 동적 대역폭 요구를 지원하는 최대-최소 흐름제어)

  • Cho, Hyug-Rae;Chong, Song;Jang, Ju-Wook
    • Journal of Institute of Control, Robotics and Systems
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    • v.6 no.8
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    • pp.638-651
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    • 2000
  • When the bandwidth resources in a packet-switched network are shared among sessions by MAX-MIN flow control each session is required to transmit its data into the network subject to the MAX-MIN fair rate which is solely determined by network loadings. This passive behavior of sessions if fact can cause seri-ous QoS(Quality of Service) degradation particularly for real-time multimedia sessions such as video since the rate allocated by the network can mismatch with what is demanded by each session for its QoS. In order to alleviate this problem we extend the concept of MAX-MIN fair bandwidth allocations as follows: Individual bandwidth demands are guaranteed if the network can accommodate them and only the residual network band-width is shared in the MAX-MIN fair sense. On the other hand if sum of the individual bandwidth demands exceeds the network capacity the shortage of the bandwidth is shared by all the sessions by reducing each bandwidth guarantee by the MAX-MIN fair division of the shortage. we present a novel flow control algorithm to achieve this extended MAX-MIN fairness and show that this algorithm can be implemented by the existing ATM ABR service protocol with minor changes. We not only analyze the steady state asymptotic stability and convergence rate of the algorithm by appealing to control theories but also verify its practical performance through simulations in a variety of network scenarios.

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