• 한국정보과학회논문지:시스템및이론
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• 제30권3_4호
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• pp.186-193
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• 2003

최근 몇 년 동안 디지털 시스템이 복잡성은 아주 빠르게 증가하고 있다. 비록 반도체 제조업자들이 제품에 대한 신뢰성을 높이려고 노력하고 있지만 어느 때에 시스템이 어딘가에서 결함이 발생할 것이라는 것을 알기는 불가능하다. 이렇듯이 회로가 복잡화함에 따라 테스트 생성(test generation)에 대한 잘 정리되어 있고 자동화된 방법이 필요하게 되었다. 하지만 현재 광범위하게 사용하고 있는 방법중 대부분은 한번에 하나씩의 패턴만을 넣어서 처리하는 방식이다. 이는 각각의 결함에 대해서 탐색하는데 많은 시간을 낭비하게 된다. 본 논문에서는 Exhaustive 방법을 사용하는 테스트 패턴 생성 방법 중에서 분할 기법을 적용하여 테스트 패턴을 생성한다. 또한 이 패턴을 이용하여 병렬로 패턴을 삽입함으로써 더욱 빠르게 결함을 발견할 수 있는 방법을 설계 및 구현한다.

• 한국항공우주학회지
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• 제50권11호
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• pp.791-800
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• 2022

능동 진동 제어 시스템(Active vibration control system, AVCS)을 이용하여 헬리콥터 기체의 능동 진동 제어 시 우수한 진동 제어 성능을 얻기 위하여서는 진동 상쇄 하중 발생기의 개수, 위치 및 하중 방향의 조합의 최적화가 중요하다. 따라서 고려 가능한 모든 하중 발생기의 조합에 대하여 헬리콥터 기체에 대한 AVCS의 진동 제어 성능을 조사하기 위해 Exhaustive 시험 기법을 적용한 AVCS 프레임워크를 구축하였다. 로터 진동 하중 해석, 기체 진동 응답 해석 및 AVCS 시뮬레이션 연구를 수행하기 위해 DYMORE II, MSC.NASTRAN 및 MATLAB Simulink 등 다양한 프로그램을 사용하였다. 이를 이용하여 비행 속도 158 knots의 UH-60A 헬리콥터에 대한 AVCS 적용을 위한 CRFG 조합을 최적화하였다. 최적의 CRFG 조합이 적용된 AVCS를 통해 UH-60A 헬리콥터의 4P 기체 진동 응답을 능동 제어한 결과, 기체의 주요 위치에서 4P 기체 진동 응답이 19.35~98.07%만큼 감소될 수 있었다.

• 한국컴퓨터산업학회논문지
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• 제6권2호
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• pp.295-304
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• 2005

본 논문에서는 워드지향 메모리 내에서 셀 사이의 커플링 결함을 검출하기 위한 고갈 테스트 발생(exhaustive test generation) 문제를 연구하였다. 셀 사이의 거플링 결함 모델에 따르면 n 워드를 갖는 메모리 내에서 w-비트 메모리 내용 또는 내용의 변화는 메모리 내의 s-1 워드 내용에 따라 영향을 받는다. 이때 검사 패턴 구성을 위한 최적의 상호작용 방법을 제안 하였으며, 제안한 검사 결과의 체계적인 구조는 간단한 BIST로 구현하였다.

• 대한전자공학회논문지
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• 제18권3호
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• pp.52-57
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• 1981

본 논문은 회로의 복잡성이 증가됨에 따른 신뢰도와 개선과 유지보수에 대한 효율성을 높이기 위한 연구로서 측정이 가능한 작은 회로 블럭을 모듈 단위로 설계하여 이들의 조합으로 디지틀 시스템을 구성하였다. 이는 측정상에 신호 발생기와 신호 해석기가 필요치 않고 모듈 단위로 완전 측정되기 때문에 높은 신뢰도와 짧은 측정 시간을 갖는다.

• International Journal of Aeronautical and Space Sciences
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• 제1권2호
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• pp.30-42
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• 2000

On-orbit thermal environment test of KOMPSAT was performed in early 1999. An analysis of the test data are addressed in this paper. For the thermal-environmental simulation of spacecraft bus, an artificial heating through the radiator zones and onto some critical heat-dissipating electronic boxes was made by Absorbed-heat Flux Method. Test data obtained in terms of temperature history were reduced into flight heater duty cycles and converted into the total electrical power required for spacecraft thermal control. Verification result of flight heaters dedicated to the bus thermal control is presented. Additionally, an exhaustive heating-control process for maintaining the spacecraft thermally safe and for realistic simulation of the orbital-thermal environment during the test are graphically shown. Qualitative suggestions to post-test model correlation are given in consequency of the analysis.

• Nuclear Engineering and Technology
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• 제50권4호
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• pp.570-581
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• 2018

Recently, a software program has been used in nuclear power plants (NPPs) to digitalize many instrumentation and control systems. To guarantee NPP safety, the reliability of the software used in safetycritical instrumentation and control systems must be quantified and verified with proper test cases and test environment. In this study, a software testing method using a simulation-based software test bed is proposed. The test bed is developed by emulating the microprocessor architecture of the programmable logic controller used in NPP safety-critical applications and capturing its behavior at each machine instruction. The effectiveness of the proposed method is demonstrated via a case study. To represent the possible states of software input and the internal variables that contribute to generating a dedicated safety signal, the software test cases are developed in consideration of the digital characteristics of the target system and the plant dynamics. The method provides a practical way to conduct exhaustive software testing, which can prove the software to be error free and minimize the uncertainty in software reliability quantification. Compared with existing testing methods, it can effectively reduce the software testing effort by emulating the programmable logic controller behavior at the machine level.

• ETRI Journal
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• 제39권3호
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• pp.364-372
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• 2017

For the reliability of controllers in a software defined network (SDN), a dynamic and self-learning schedule method (DSL) is proposed. This method is original and easy to deploy, and optimizes the combination of multiple controllers. First, we summarize multiple controllers' combinations and schedule problems in an SDN and analyze its reliability. Then, we introduce the architecture of the schedule method and evaluate multi-controller reliability, the DSL method, and its optimized solution. By continually and statistically learning the information about controller reliability, this method treats it as a metric to schedule controllers. Finally, we compare and test the method using a given testing scenario based on an SDN network simulator. The experiment results show that the DSL method can significantly improve the total reliability of an SDN compared with a random schedule, and the proposed optimization algorithm has higher efficiency than an exhaustive search.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 B
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• pp.1380-1382
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• 1996

In this paper, a motion estimation module is made with ADSP-21020 based on MPEG-2 which is an international standard for moving picture compression. And, the block matching algorithm used as motion estimation method is easy for an hardware implementation. The ADSP-21020 of Analog Device is used for a main control processor. We used three block matching method (exhaustive search method, 2D-logarithmic search method, three step search method) for software simulation and implemented the three step search method to hardware. For the test of the estimation module, we used ping pong image sequences and mobile and calendar image sequences.

• Nuclear Engineering and Technology
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• 제52권7호
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• pp.1462-1470
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• 2020

Reliability in safety-critical systems and equipment is of vital importance, so the probabilistic safety assessment (PSA) has been widely used for many years in the nuclear industry to address reliability in a quantitative manner. As many nuclear power plants (NPPs) become digitalized, evaluating the reliability of safety-critical software has become an emerging issue. Due to a lack of available methods, in many conventional PSA models only hardware reliability is addressed with the assumption that software reliability is perfect or very high compared to hardware reliability. This study focused on developing a new method of safety-critical software reliability quantification, derived from hardware-software integrated environment testing. Since the complexity of hardware and software interaction makes the possible number of test cases for exhaustive testing well beyond a practically achievable range, an importance-oriented testing method that assures the most efficient test coverage was developed. Application to the test of an actual NPP reactor protection system demonstrated the applicability of the developed method and provided insight into complex software-based system reliability.

• 대한전기학회논문지:시스템및제어부문D
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• 제49권6호
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• pp.322-329
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• 2000

BIST(Built-in Self Test) has been considered as the most promising DFT(design-for-test) scheme for the present and future test strategy. The most serious problem in applying BIST(Built-in Self Test) into a large circuit is the excessive increase in test time. This paper is focused on this problem. We proposed a new BIST construction scheme which uses a parallel divide-and-conquer method. The circuit division is performed with respect to some internal nodes called test points. The test points are selected by considering the nodal connectivity of the circuit rather than the testability of each node. The test patterns are generated by only one linear feedback shift register(LFSR) and they are shared by all the divided circuits. Thus, the test for each divided circuit is performed in parallel. Test responses are collected from the test point as well as the primary outputs. Even though the divide-and-conquer scheme is used and test patterns are generated in one LFSR, the proposed scheme does not lose its pseudo-exhaustive property. We proposed a selection procedure to find the test points and it was implemented with C/C++ language. Several example circuits were applied to this procedure and the results showed that test time was reduced upto 1/2151 but the increase in the hardware overhead or the delay increase was not much high. Because the proposed scheme showed a tendency that the increasing rates in hardware overhead and delay overhead were less than that in test time reduction as the size of circuit increases, it is expected to be used efficiently for large circuits as VLSI and ULSI.