• Journal of KIISE:Computer Systems and Theory
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• v.30 no.3_4
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• pp.186-193
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• 2003

In recent years the complexity of digital systems has increased dramatically. Although semiconductor manufacturers try to ensure that their products are reliable, it is almost impossible not to have faults somewhere in a system at any given time. As complexity of circuits increases, the necessity of more efficient organized and automated methods for test generation is growing. But, up to now, most of popular and extensive methods for test generation nay be those which sequentially produce an output for an input pattern. They inevitably require a lot of time to search each fault in a system. In this paper, corresponding test patterns are generated through the partitioning method among those based on the exhaustive method. In addition, the method, which can discovers faults faster than other ones that have been proposed ever by inserting a pattern in parallel, is designed and implemented.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.50 no.11
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• pp.791-800
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• 2022

The number and locations of force generators and their force directions of Active Vibration Control System(AVCS) are important to maximize the airframe vibration reduction performance of helicopters. The present AVCS simulation using an exhaustive test method attempts to determine the best number and locations of force generators and their force directions for maximization of the airframe vibration reduction performance of UH-60A helicopter at 158 knots. The 4P hub vibratory loads of the UH-60A helicopter are calculated using DYMORE II, a nonlinear multibody dynamics analysis code, and MSC.NASTRAN is used to predict the vibration responses of the UH-60A airframe. The AVCS framework with an exhaustive test method is constructed using MATLAB Simulink. As a result, when applying AVCS with the optimal combination of the force generators, the 4P airframe vibration responses of UH-60A helicopter are reduced by from 19.35% to 98.07% compared to the baseline results without AVCS.

• Journal of the Korea Computer Industry Society
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• v.6 no.2
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• pp.295-304
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• 2005

This paper presents the problem of exhaustive test generation for detection of coupling faults between cells in word-oriented memories. According to this fault model, contents of any w-bit memory word in a memory with n words, or ability tochange this contents, is influenced by the contents of any other s-1 words in the memory. A near optimal iterative method for construction of test patterns is proposed The systematic structure of the proposed test results in simple BIST implementations.

• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.3
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• pp.52-57
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• 1981

This paper deals with the development of a design approach to generate easily testable complex digital systems. As the technique is based on small testable building blocks (submodule) with the exhaustive testing circuits, it is not necessary for any automatic test equipment and signature analyzer. As a result ,the test time which is determined not by circuit complexity but sixte of the tarprest submodule, is not exhaustive and also, the circuit reliability is very high.

• International Journal of Aeronautical and Space Sciences
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• v.1 no.2
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• pp.30-42
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• 2000

On-orbit thermal environment test of KOMPSAT was performed in early 1999. An analysis of the test data are addressed in this paper. For the thermal-environmental simulation of spacecraft bus, an artificial heating through the radiator zones and onto some critical heat-dissipating electronic boxes was made by Absorbed-heat Flux Method. Test data obtained in terms of temperature history were reduced into flight heater duty cycles and converted into the total electrical power required for spacecraft thermal control. Verification result of flight heaters dedicated to the bus thermal control is presented. Additionally, an exhaustive heating-control process for maintaining the spacecraft thermally safe and for realistic simulation of the orbital-thermal environment during the test are graphically shown. Qualitative suggestions to post-test model correlation are given in consequency of the analysis.

• Nuclear Engineering and Technology
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• v.50 no.4
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• pp.570-581
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• 2018

Recently, a software program has been used in nuclear power plants (NPPs) to digitalize many instrumentation and control systems. To guarantee NPP safety, the reliability of the software used in safetycritical instrumentation and control systems must be quantified and verified with proper test cases and test environment. In this study, a software testing method using a simulation-based software test bed is proposed. The test bed is developed by emulating the microprocessor architecture of the programmable logic controller used in NPP safety-critical applications and capturing its behavior at each machine instruction. The effectiveness of the proposed method is demonstrated via a case study. To represent the possible states of software input and the internal variables that contribute to generating a dedicated safety signal, the software test cases are developed in consideration of the digital characteristics of the target system and the plant dynamics. The method provides a practical way to conduct exhaustive software testing, which can prove the software to be error free and minimize the uncertainty in software reliability quantification. Compared with existing testing methods, it can effectively reduce the software testing effort by emulating the programmable logic controller behavior at the machine level.

• ETRI Journal
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• v.39 no.3
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• pp.364-372
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• 2017

For the reliability of controllers in a software defined network (SDN), a dynamic and self-learning schedule method (DSL) is proposed. This method is original and easy to deploy, and optimizes the combination of multiple controllers. First, we summarize multiple controllers' combinations and schedule problems in an SDN and analyze its reliability. Then, we introduce the architecture of the schedule method and evaluate multi-controller reliability, the DSL method, and its optimized solution. By continually and statistically learning the information about controller reliability, this method treats it as a metric to schedule controllers. Finally, we compare and test the method using a given testing scenario based on an SDN network simulator. The experiment results show that the DSL method can significantly improve the total reliability of an SDN compared with a random schedule, and the proposed optimization algorithm has higher efficiency than an exhaustive search.

• Proceedings of the KIEE Conference
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• 1996.07b
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• pp.1380-1382
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• 1996

In this paper, a motion estimation module is made with ADSP-21020 based on MPEG-2 which is an international standard for moving picture compression. And, the block matching algorithm used as motion estimation method is easy for an hardware implementation. The ADSP-21020 of Analog Device is used for a main control processor. We used three block matching method (exhaustive search method, 2D-logarithmic search method, three step search method) for software simulation and implemented the three step search method to hardware. For the test of the estimation module, we used ping pong image sequences and mobile and calendar image sequences.

• Nuclear Engineering and Technology
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• v.52 no.7
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• pp.1462-1470
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• 2020

Reliability in safety-critical systems and equipment is of vital importance, so the probabilistic safety assessment (PSA) has been widely used for many years in the nuclear industry to address reliability in a quantitative manner. As many nuclear power plants (NPPs) become digitalized, evaluating the reliability of safety-critical software has become an emerging issue. Due to a lack of available methods, in many conventional PSA models only hardware reliability is addressed with the assumption that software reliability is perfect or very high compared to hardware reliability. This study focused on developing a new method of safety-critical software reliability quantification, derived from hardware-software integrated environment testing. Since the complexity of hardware and software interaction makes the possible number of test cases for exhaustive testing well beyond a practically achievable range, an importance-oriented testing method that assures the most efficient test coverage was developed. Application to the test of an actual NPP reactor protection system demonstrated the applicability of the developed method and provided insight into complex software-based system reliability.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.6
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• pp.322-329
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• 2000

BIST(Built-in Self Test) has been considered as the most promising DFT(design-for-test) scheme for the present and future test strategy. The most serious problem in applying BIST(Built-in Self Test) into a large circuit is the excessive increase in test time. This paper is focused on this problem. We proposed a new BIST construction scheme which uses a parallel divide-and-conquer method. The circuit division is performed with respect to some internal nodes called test points. The test points are selected by considering the nodal connectivity of the circuit rather than the testability of each node. The test patterns are generated by only one linear feedback shift register(LFSR) and they are shared by all the divided circuits. Thus, the test for each divided circuit is performed in parallel. Test responses are collected from the test point as well as the primary outputs. Even though the divide-and-conquer scheme is used and test patterns are generated in one LFSR, the proposed scheme does not lose its pseudo-exhaustive property. We proposed a selection procedure to find the test points and it was implemented with C/C++ language. Several example circuits were applied to this procedure and the results showed that test time was reduced upto 1/2151 but the increase in the hardware overhead or the delay increase was not much high. Because the proposed scheme showed a tendency that the increasing rates in hardware overhead and delay overhead were less than that in test time reduction as the size of circuit increases, it is expected to be used efficiently for large circuits as VLSI and ULSI.