• Title/Summary/Keyword: Executions

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Tracking Control of Ball and Plate System via Integrated Fuzzy Controllers (결합된 퍼지 제어기를 이용한 볼과 플레이트 시스템에서의 추정제어기 설계)

  • Seo, Min-Seok;Hyun, Chang-Ho;Park, Mig-Noon
    • Proceedings of the KIEE Conference
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    • 2006.10c
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    • pp.223-225
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    • 2006
  • A ball moving on a beam is a typical nonlnear dynamic system, which is often adopted to proof test diverse control schemes. Ball and plate system is the extension of the traditional ball and beam problem that moves a metal ball on a rigid plate. In this paper, a trajectory planning and tracking problem is proposed for ball and plate system, which is to control the ball from a point to another without hitting the obstacles. Our scheme is composed of three controllers, TS type optimal path tracking controller, mandani type obstacle avoidance controller and trajectory planning controller that determines the desired trajectory. But this type of construction can give rise to chattering executions. Because the difference of contributions from concurrent controllers can cause behaviors unsmoothly. We propose fuzzy pid supervision control1er to handle this problem.

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Performance Evaluation of Real-time Mechanisms for Real-time Embedded Linux (실시간 임베디드 리눅스의 실시간 메커니즘 성능 분석)

  • Koh, Jae-Hwan;Choi, Byoung-Wook
    • Journal of Institute of Control, Robotics and Systems
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    • v.18 no.4
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    • pp.337-342
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    • 2012
  • This paper presents performance evaluation of real-time mechanisms for real-time embedded linux. First, we presents process for implementing open-source real-time embedded linux namely RTAI and Xenomai. These are real-time extensions to linux kernel and we implemented real-time embedded linux over the latest linux kernel. Measurements of executions of real-time mechanisms for each distribution are performed to give a quantitative comparison. Performance evaluations are conducted in kernel space about repeatability of periodic task, response time of Semaphore, FIFO, Mailbox and Message queue in terms of inter-task communication for each distribution. These rules can be helpful for deciding which real-time linux extension should be used with respect to the requirements of the real-time applications.

Design of an ALU and a Shifter for RISC (RISC용 ALU와 시프터의 설계)

  • 최병윤;최상훈;이문기
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.28B no.7
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    • pp.520-534
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    • 1991
  • This paper describes the design of an ALU and a shifter for RISC. The RISC datapath is designed to have a 4-stage pipeline and a 20 MHz operating frequency. The ALU makes use of the 32-bit BLC adder which has the characteristics of high speed ane regular structuer and executes the arithmetic instructions-addition and subtraction- and the logical instructions-AND, OR, and XOR. Additionally, multiplication is possible by iterative executions of step instructions to perform shift and add operations. The shifter is implemented by using the modified of funnel shifter. The shifter is able to perform the arithmetic andlogical shift instructions without maskiog. Moreover, it carries out data align operation which conforms to big endian byte address. The logical operation of the desinged ALU and the shifter were simulated using YSLOG and VLSIsim. SPICE simulation results using 1.2um double metal process parameters show that the ALU and shifter have a delay time of 15.9NS and 9.9NS, respectively. Therefore, the ALU and the shifter operates correctly above 20[ MHz ] click ferquency and are composed of about 7K and 15K teansistors, respectively.

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A VLSI implementation of 32-bit RISC embedded controller (내장형 32비트 RISC 콘트롤러의 VLSI 구현)

  • 이문기;최병윤;이승호
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.31A no.10
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    • pp.141-151
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    • 1994
  • this paper describes the design and implementation of a RISC processor for embedded control systems. This RISC processor integrates a register file, a pipelined execution unit, a FPU interface, a memory interface, and an instruction prefetcher. Its characteristics include both single cycle executions of most instructions in a 2 phase 20 MHz frequency and the worst case interrupt latency of 7 cycles with the vectored interrupt handling that makes it possible to be applicable to the real time processing system. For efficient handling of multi-cycle instructions, data stationary hardwired control scheme equippedwith cycle counter was used. This chip integrates about 139K transistors and occupies 9.1mm$\times$9.1mm in a 1.0um DLM CMOS technology. The power dissipation is 0.8 Watts from a 5V supply at 20 MHz operation.

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Analysis on the Calculation of Plasma Medium with Parallel SO-FDTD Method

  • Duan, Xule;Yang, Hong Wei;Kong, Xiangkun;Liu, Han
    • ETRI Journal
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    • v.31 no.4
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    • pp.387-392
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    • 2009
  • This paper introduces a novel parallel shift operator finite-difference time-domain (SO-FDTD) method for plasma in the dispersive media. We calculate the interaction between the electromagnetic wave of various frequencies and non-magnetized plasma by using the parallel SO-FDTD method. Then, we compare the results,which are calculated with serial and parallel SO-FDTD executions to obtain the speedup ratio and validate the parallel execution. We conclude that the parallel SO method has almost the same precision as the serial SO method, while the parallel approach expands the scope of memory and reduces the CPU time.

Development of MARS Transient Analyzer

  • Hwang, M.K.;Kim, K.D.;Jeong, J.-J.;Lee, Y.J.;Chung, B.D.
    • Proceedings of the Korean Nuclear Society Conference
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    • 2002.10a
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    • pp.155.2-155
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    • 2002
  • A visual environment for system analysis codes (hereinafter called "ViSA") has been developed to support code users in their input preparations, code executions, and output interpretations. ViSA provides a more convenient way for base input data generation and modification on a user-friendly basis. It also provides on-line graphical displays to give an in-depth understanding of transient thermal-hydraulic behaviors in nuclear power plants. This paper presents the main features of ViSA.

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Analysis of Some Strange Behaviors of Floating Point Arithmetic using MATLAB Programs (MATLAB을 이용한 부동소수점 연산의 특이사항 분석)

  • Chung, Tae-Sang
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.56 no.2
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    • pp.428-431
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    • 2007
  • A floating-point number system is used to represent a wide range of real numbers using finite number of bits. The standard the IEEE adopted in 1987 divides the range of real numbers into intervals of [$2^E,2^{E+1}$), where E is an Integer represented with finite bits, and defines equally spaced equal counts of discrete numbers in each interval. Since the numbers are defined discretely, not only the number representation itself includes errors but in floating-point arithmetic some strange behaviors are observed which cannot be agreed with the real world arithmetic. In this paper errors with floating-point number representation, those with arithmetic operations, and those due to order of arithmetic operations are analyzed theoretically with help of and verification with the results of some MATLAB program executions.

Object-oriented model management support system

  • Park, Sung-Joo;Kwon, O-Byung
    • Proceedings of the Korean Operations and Management Science Society Conference
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    • 1990.04a
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    • pp.42-48
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    • 1990
  • Increasing concerns about model management system lead to studies of user friendliness and model executions. This paper presents model as object's method based on the Object-Oriented Concepts which makes it possible to represent model's operation and enables general decision makers to identify and select more appropriate models. This capability reduces the semantic gap between decision maker and model builder. This view is also able to execute models by way of automatic Ada code generation and specific LP formulation for LINDO. A prototype system is implemented in Pascal.

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The Generation of Transaction Monitor Modules from a Transaction-Oriented Interface Protocol Description (트랜잭션 중심의 인터페이스 프로토콜 기술로부터 트랜잭션 모니터 모듈의 생성)

  • 윤창렬;장경선;조한진
    • Journal of KIISE:Computing Practices and Letters
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    • v.8 no.6
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    • pp.756-764
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    • 2002
  • The verification portion of SoC design consumes about 70% of total design effort. To reduce the verification effort and time, it is necessary and desirable to raise the level of SoC design verifications level from the signal or cycle level to the transaction. This paper describes a generation method of transaction monitor modules that monitor interface signals, logging the transaction executions, and report transaction errors. The input of the generation method is a transaction-oriented interface protocol description.

Recovery Executions of Collapsed Face in Weak Zone (저토피 연약대 터널막장 붕락에 대한 갱내 보강사례)

  • Lee, Hong-Sung;Woo, Sang-Baik;Choi, Byung-Kil;Park, Kyung-Wook
    • 기술발표회
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    • s.2006
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    • pp.331-341
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    • 2006
  • 터널 설계시 일반적으로 지반조사와 물리탐사를 시행하여 지층에 따른 적절한 터널 지보패턴을 설정하고 있으나, 다양한 지반 및 지질특성과 설계단계에서 미쳐 발견되지 못한 단층등의 연약대로 인하여 시공시 터널내에서 종종 붕락사고가 발생하고 있다. 터널 굴착시 발생하는 붕락은 터널의 안정성 저하 및 공기 지연 등의 큰 문제점들을 발생시키므로 조기에 적절한 보강방안이 요구된다. 본 논문에서는 터널 굴착시 발생한 두개의 붕락사고에 대해서 붕락원인과 붕괴유형을 파악하고 현장 여건에 맞는 신속한 보강대책을 제시하고 시공한 보강사례이다. 향 후 본 사례와 유사한 터널붕락사고가 발생할 경우 보강설계 및 보강방안을 계획.수립하는데 유용한 참고자료가 될 것이다.

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