• Proceedings of the Korean Operations and Management Science Society Conference
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• 2003.05a
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• pp.808-813
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• 2003

Maintaining agility and responsiveness m designing and manufacturing activities are the key issues for manufacturing companies to cope with global competition. Distributed design and control systems are regarded as an efficient solution for agility and responsiveness. However, distributed nature of a manufacturing system complicates production activities such as design, simulation, scheduling, and execution control. Especially, existing simulation systems have limited external integration capabilities, which make it difficult to implement complex control mechanisms for the distributed manufacturing systems. Moreover, integration and coupling of heterogeneous components and models are commonly required for the simulation of complex distributed systems. In this paper, a collaborative and adaptive simulation architecture is proposed as an open framework for simulation and analysis of the distributed manufacturing enterprises. By incorporating agents with their distributed characteristics of autonomy, intelligence, and goal-driven behavior, the proposed agent-based simulation architecture can be easily adapted to support the agile and distributed manufacturing systems. The architecture supports the coordination and cooperation relations, and provides a communication middleware among the participants in simulation.

• Proceedings of the KSME Conference
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• 2002.08a
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• pp.67-70
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• 2002

In the present study a pre/post-processor program has been developed to be used with a general CFD code. This program is capable of performing the basic functions of the pre/post-processing, which include mesh generation and post processing plots. Also through perspective projection, this program can be used to check the quality of generated mesh by moving around inside the mesh. The smoke visualization can be also performed with the present program to visualize the smoke behavior in the case of fire simulation. The examples of the program execution are given in paper.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.12
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• pp.5694-5711
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• 2017

The technology of cloud computing is growing very quickly, thus it is required to manage the process of resource allocation. In this paper, load balancing algorithm based on honey bee behavior (LBA_HB) is proposed. Its main goal is distribute workload of multiple network links in the way that avoid underutilization and over utilization of the resources. This can be achieved by allocating the incoming task to a virtual machine (VM) which meets two conditions; number of tasks currently processing by this VM is less than number of tasks currently processing by other VMs and the deviation of this VM processing time from average processing time of all VMs is less than a threshold value. The proposed algorithm is compared with different scheduling algorithms; honey bee, ant colony, modified throttled and round robin algorithms. The results of experiments show the efficiency of the proposed algorithm in terms of execution time, response time, makespan, standard deviation of load, and degree of imbalance.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.6
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• pp.1040-1048
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• 1987

We propose a hardware architecture called Multiring which is applicable for various geometrical operations on rectilinear objects such as design rule checking in VLSI layout and many image processing operations including noise suppression and coutour extraction. It has both a fast execution speed and extremely high flexibility. The whole architecture is mainly divided into four parts` I/O between host and Multiring, ring memory, linear processor array and instruction decoder. Data transmission between host and Multiring is bit serial thereby reducing the bandwidth requirement for teh channel and the number of external pins, while each row data in the bit map stored in ring memory is processed in the corresponding processor in full parallelism. Each processor is simultaneously configured by the instruction decoder/controller to perform one of the 16 basic instructions such as Boolean (AND, OR, NOT, and Copy), geometrical(Expand and Shrink), and I/O operations each ring cycle, which gives Multiring maximal flexibility in terms of design rule change or the instruction set enhancement. Correct functional behavior of Multiring was confirmed by successfully running a software simulator having one-to-one structural correspondence to the Multiring hardware.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.29 no.3
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• pp.119-127
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• 2006

In this paper, we present a systematic approach to translating BPML(Business Process Modeling Language) into the ${\pi}-Calculus$. BPML is an executable business process modeling language, like BPEL4WS(Business Process Execution Language for Web Services). It is difficult to find a systematic approach to formalizing these languages; but, by formalizing them, the behavior of the processes can be analyzed and compared so that optimal processes can be designed. For this formalization, we analyzed the activity types and contexts of BPML and suggested the definitions of semantics for each type and context by using the ${\pi}-Calculus$. In addition, we have shown the usefulness of our formalization scheme in that a typical order fulfillment process represented in BPML can be translated into the ${\pi}-Calculus$.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.12
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• pp.2484-2491
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• 2009

This paper proposes robust state feedback control of asynchronous sequential machines with model uncertainty. The considered asynchronous machine is deterministic, but its state transition function is partially known before executing a control process. The main objective is to derive the existence condition for a corrective controller for which the behavior of the closed-loop system can match a prescribed model in spite of uncertain transitions. The proposed control scheme also has learning ability. The controller perceives true state transitions as it undergoes corrective actions and reflects the learned knowledge in the next step. An adaptation is made such that the controller can have the minimum number of state transitions to realize a model matching procedure. To demonstrate control construction and execution, a VHDL and FPGA implementation of the proposed control scheme is presented.

• Proceedings of the Korean Information Science Society Conference
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• 2000.10a
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• pp.436-438
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• 2000

다양한 실행 경로가 존재하는 실시간 시스템을 이해하기 위해 시스템의 정적 정보와 함께 동정 정보가 사용자에게 적절히 제공되어야 한다. 본 논문은 정적 정보와 동적 정보를 표현하기 위해 SRL(System Representation Language)을 사용한다. 정적 정보는 SRL 노드를 분석해서 얻고 동적 정보는 SRL을 실행함으로 얻는다. SRL의 가상 실행은 시스템 독립적인 자바 가상 기계를 통해 이루어진다. 가상 실행은 순방향뿐만 아니라 역방향으로도 이루어진다. SRL 실행 라이브러리는 순.역방향 실행을 위해 SRL 각 구문의 의미 규칙에 맞게 정의하며 자바 가상 기계를 통해 실행되는 클래스 파일로 컴파일된다. 메모리에 로딩된 SRL은 SRL 실행 라이브러리를 동적으로 호출하여 가상 실행을 이룬다. 동적 실행을 통해 추출된 동적 정보는 SRL에 포함된다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.4 no.4
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• pp.452-474
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• 2010

Formidable growth of Internet technologies has revealed challenging issues about its scale and performance evaluation. Modeling and simulation play a central role in the evaluation of the behavior and performance of the large-scale network systems. Large numbers of nodes affect simulation performance, simulation execution time and scalability in a weighty manner. Most of the existing simulators have numerous problems such as size, lack of system theoretic approach and complexity of modeled network. In this work, a scalable discrete-event modeling approach is described for studying networks' scalability and performance traits. Key fundamental attributes of Internet and its protocols are incorporated into a set of simulation models developed using the Discrete Event System Specification (DEVS) approach. Large-scale network models are simulated and evaluated to show the benefits of the developed network models and approaches.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.359-362
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• 2000

In this paper, we propose a test pattern generation algorithm on the basis of the identification of undetectable faults for Speed-Independent(SI) asynchronous control circuits. The proposed methodology generates tests from the specification of a target circuit, which describes the behavior of the circuit in the form of Signal Transition Graph (STG). The proposed identification method uses only topological information of a target circuit and reachability information of a fault-free circuit, which is generated in the form of Binary Decision Diagram(BDD) during pre-processing. Experimental results show that high fault coverage over single input stuck-at fault model is obtained for several synthesized SI circuits and the use of the identification process as a preprocessing decreases execution time of the proposed test generation with negligible costs.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.21 no.45
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• pp.101-112
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• 1998

Data mining, which is also referred to as knowledge discovery in database, means a process of nontrivial extraction of implicit, previously unknown and potentially useful information (such as knowledge rules, constraints, regularities) from data in databases. The discovered knowledge can be applied to information management, decision making, and many other applications. In this paper, a new data mining problem, discovering sequential patterns, is proposed which is to find all sequential patterns using sampling method. Recognizing that the quantity of database is growing exponentially and transaction database is frequently updated, sampling method is a fast algorithm reducing time and cost while extracting the trend of customer behavior. This method analyzes the fraction of database but can in general lead to results of a very high degree of accuracy. The relaxation factor, as well as the sample size, can be properly adjusted so as to improve the result accuracy while minimizing the corresponding execution time. The superiority of the proposed algorithm will be shown through analyzing accuracy and efficiency by comparing with Apriori All algorithm.