• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.129-134
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• 2005

Electroplating copper is the important role in formation of 3D stacking interconnection in SiP (System in Package). The I-V characteristics curves are investigated at different electrolyte conditions. Inhibitor and accelerator are used simultaneously to investigate the effects of additives. Three different sizes of via are tested. All via were prepared with RIE (reactive ion etching) method. Via's diameter are 50, 75, $100{\mu}m$ and the height is $100{\mu}m$. Inside via, Ta was deposited for diffusion barrier and Cu was deposited fer seed layer using magnetron sputtering method. DC, pulse and pulse revere current are used in this study. With DC, via cannot be filled without defects. Pulse plating can improve the filling patterns however it cannot completely filled copper without defects. Via was filled completely without defects using pulse-reverse electroplating method.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.9 no.5
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• pp.463-469
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• 1999

The potassium lithium niobate $K_3$$Li_2$$Nb_5$$O_{15}$ single crystals were growing in $K_x$$Li_{1-x}$$NbO_3$ (x = 0.4~0.6) chemical formular by the Czorchralski method. Crystal growth is studied in two orientations with growth along a-axis and c-axis. We have subjected this crystal to x-ray diffraction studies and found that they are single-crystalline and belong to tetragonal system with the lattice parameters a = b = 12.577 $\AA$ and c = 3.997$\AA$. The temperature dependence of dielectric constant was measured in the region of the phase transition. Curie temperature and diffuseness of phase transition are influenced by composition concentration. The composition and cation distribution of ferroelectric TB-type niobate crystals has a strong influence on the ferroelectric properties. Growth condition, optical transmittance, etching pattern and dielectric properties are presented and discussed.

• Proceedings of the KIEE Conference
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• 1998.07g
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• pp.2518-2520
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• 1998

Silicon can be reactive ion etched (RIE) either isotropically or anisotropically. In this paper, a new micromachining technology combining these two etching characteristics is proposed. In the proposed method, the fabrication steps are as follows. First. a polysilicon layer, which is used as the bottom electrode, is deposited on the silicon wafer and patterned. Then the silicon substrate is etched anisotropically to a few micrometer depth that forms a cavity. Then an PECVD oxide layer is deposited to passivate the cavity side walls. The oxide layers at the top and bottom faces are removed while the passivation layers of the side walls are left. Then the substrate is etched again but in an isotropic etch condition to form a round trench with a larger radius than the anisotropic cavity. Then a sacrificial PECVD oxide layer is deposited and patterned. Then a polysilicon structural layer is deposited and patterned. This polysilicon layer forms a pivot structure of a rocker-arm. Finally, oxide sacrificial layers are etched away. This new micromachining technology is quite simpler than conventional method to fabricate joint structures, and the devices that are fabricated using this technology do not require a flexing structure for motion.

• Journal of the Semiconductor & Display Technology
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• v.4 no.2 s.11
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• pp.39-43
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• 2005

In the study, in order to deposit TaN thin film for diffusion barrier and bottom electrode we made the Plasma Assisted ALD equipment and confirmed the electrical characteristics of TaN thin films grown PAALD method. Plasma Assisted ALD equipment depositing TaN thin film using PEMAT(pentakis(ethylmethlyamino) tantalum) precursor and NH3 reaction gas is shown that TaN thin film deposited high density and amorphous phase with XRD measurement. The degree of diffusion and reaction taking place in Cu/TaN (deposited using 150W PAALD)/$SiO_{2}$/Si systems with increasing annealing temperature was estimated for MOS capacitor property and the $SiO_{2}$, (600${\AA}$)/Si system surface analysis by C-V measurement and secondary ion material spectrometer (SIMS) after Cu/TaN/$SiO_{2}$ (400 ${\AA}$) layer etching. TaN thin film deposited PAALD method diffusion barrier have a good diffusion barrier property up to 500$^{\circ}C$.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.1
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• pp.63-69
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• 2000

The high-$T_c$ Superconducting (HTS) antenna which consists of "H" type resonator has the benefits for the miniaturization of antenna in comparison with the microstrip antenna of the similar dimension. To fabricate the "H" type antenna, HTS $YBa_2Cu_3O_{7-x}$ (YBCO) thin films were deposited on MgO substrates using rf-magnetron sputtering. Standard etching processes were performed for the patterning of the "H" type antenna. For comparison between normal conducting antennas and superconducting antennas, the gold antennas with the same dimension were also fabricated. An aperture coupling was used for impedance matching between $50{\Omega}$ feed line and HTS radiating patch. The diverse experimental results were reported in terms of the resonant frequency, the return loss and the characteristics impedance. The "H" type superconducting antenna showed the performance of 1.36 in SWR, 24% in efficiency, and 14.6 dB in the return loss superior of the normal conducting counterpart.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.8-22
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• 2014

In the past few decades, CMOS logic technologies and devices have been successfully developed with the steady miniaturization of the feature size. At the sub-30-nm CMOS technology nodes, one of the main hurdles for continuously and successfully scaling down CMOS devices is the parametric failure caused by random variations such as line edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). The characteristics of each random variation source and its effect on advanced device structures such as multigate and ultra-thin-body devices (vs. conventional planar bulk MOSFET) are discussed in detail. Further, suggested are suppression methods for the LER-, RDF-, and WFV-induced threshold voltage (VTH) variations in advanced CMOS logic technologies including the double-patterning and double-etching (2P2E) technique and in advanced device structures including the fully depleted silicon-on-insulator (FD-SOI) MOSFET and FinFET/tri-gate MOSFET at the sub-30-nm nodes. The segmented-channel MOSFET (SegFET) and junctionless transistor (JLT) that can suppress the random variations and the SegFET-/JLT-based static random access memory (SRAM) cell that enhance the read and write margins at a time, though generally with a trade-off between the read and the write margins, are introduced.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.7
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• pp.1182-1190
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• 2001

In this paper, microstrip photonic bandgap (PBG) structure with special perforation patterns etched on the line itself is analyzed and optimized in shape, then used for harmonic tuning of power amplifier. This PBG has an advantage in being fabricated and grounded. The dimension of unit lattice is enlarged vertically, but its input and output line maintain 50 Ω using tapered line. This modification from original structure can lessen possible error in etching PCB. The analysis and design of PBG structure are acquired from using EM simulation. The measured insertion loss of the final structure is 0.3 ∼0.4 dB, and its bandwidth of stopband is 6∼7 GHz. Measured results of improved characteristics by using PBG structure at the output of the power amplifier are 0.72∼0.99 dB in output power, 1.14∼7.8 % in PAE, and 1 dBc in the third IMD.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.11
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• pp.7773-7780
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• 2015

Analysis of existing kettle and its heating system has been the topic for localization technology development. Test pieces are made, polished and etched for existing kettle analysis. Surface of test pieces is observed using SEM, the kettle is verified to be made by deep drawing process from Ferrite-Perlite material. The kettle is also identified to be plated $16{\sim}49{\mu}m$ of thickness with Nickel(16%). Also heat transfer characteristics based on hot wire arrangement is investigated and optimal hot wire system is developed. Developed control system detects overheating and stops the whole system on the long operating time. Developed kettle takes the performance evaluation test for volume expansion and satisfied for standard 'KS G3602'.

• Journal of Sensor Science and Technology
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• v.22 no.5
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• pp.333-337
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• 2013

This study proposes a simply fabricated micro stator for higher output power than previously reported micro stators. The stator has been fabricated by inserting enamel coil in silicon mold formed by micro etching process. The most merits of the proposed micro stator are the simple fabrication process and high output power. Previously reported micro stators have high resistance because the micro coil is fabricated by relatively thin-film-based deposition process such as sputtering and electroplating. In addition, the previously reported micro coil has many electrical contact points for forming the coil structure. These characteristics of the micro stator can lead to low performance in output power. However, the proposed micro stator adopts commercially available enamel coil without any contact point. Therefore, the enamel coil of the proposed micro stator has low junction resistance due to the good electrical quality compared with the deposited or electroplated metal coil. Power generation tests were performed and the fabricated stator can produce 5.4 mW in 4000 RPM, $1{\Omega}$ and 0.3 mm gap. The proposed micro stator can produce larger output power than the previously reported stator spite of low RPM and the larger gap between the permanent magnet and the stator.

• Journal of the Korean Vacuum Society
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• v.7 no.2
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• pp.88-93
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• 1998

The fabrication process and emission characteristics of gated silicon field emitter arrays(FEAs) using chemical-mechanical-polishing (CMP) method are described. Novel fabrication techniques consisting of two-step dry etching with oxidation of silicon and CMP processes were developed for the formation of sharp tips and clear-cut edged gate electrodes, respectively. The gate height and aperture could be easily controlled by varying the polishing time and pressure in the CMP process. We obtained silicon FEAs having self-aligned and clear-cut edged gate electrode opening by eliminating the dishing problem during the CMP process with an oxide mask layer. The tip height of the finally fabricated FEAs was about 1.1 $\mu$m and the end radius of the tips was smaller than 100 $\AA$. The emission current meaured from the fabricated 2809 tips array was about 31 $\mu$A at a gate voltage of 80 V.