• 제어로봇시스템학회:학술대회논문집
• /
• 2004.08a
• /
• pp.1962-1965
• /
• 2004

In this paper, the new algorithm for blind adaptive decorrelating parallel interference canceller detector in direct-sequence code division multiple access (DS-CDMA) synchronous communication systems is proposed. The goal of this paper is to improve the performance of the blind adaptive decorrelating parallel interference cancellation detector (BAD/PIC). The proposed blind adaptive decorrelating detector is using optimum step-size technique bootstrap algorithm as an initial stage of PIC, which does not require a training sequence. Therefore, this algorithm has a superior view of utilizing bandwidth and reduces the complexity of computation of inversion cross-correlation matrix. The computer simulation results show that the bit error rate performance of the proposed algorithm for the new structure of detector is better than that of the other detectors such as matched filters, the conventional PIC, and the blind adaptive decorrelating PIC detector.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.47 no.8
• /
• pp.1-8
• /
• 2010

This paper models a symbol timing offset (STO) with respect to the guard period and the maximum access delay time for asynchronous multicarrier code division multiple access (MC-CDMA) uplink systems over frequency-selective multipath fading channels. Analytical derivation shows that STO causes desired signal power degradation and generates self-interferences. This effect of the STO on the average bit error rate (BER) and the effective signal-to-noise ratio (SNR) is evaluated. The approximated BER and the SNR loss caused by STO are then obtained as closed-form expressions. The tightness between the analytical result and the simulated one is verified for the different STOs and SNRs. Furthermore, the derived analytical results are verified via Monte Carlo simulations.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.5 no.10
• /
• pp.1783-1798
• /
• 2011

Recently, a cryptographic construct, called fuzzy vault, has been proposed for crypto-biometric systems, and some implementations for fingerprint have been reported to protect the stored fingerprint template by hiding the fingerprint features. In this paper, we implement the fuzzy fingerprint vault, combining fingerprint verification and fuzzy vault scheme to protect fingerprint templates. To implement the fuzzy fingerprint vault as a complete system, we have to consider several practical issues such as automatic fingerprint alignment, verification accuracy, execution time, error correcting code, etc. In addition, to protect the fuzzy fingerprint vault from the correlation attack, we propose an approach to insert chaffs in a structured way such that distinguishing the fingerprint minutiae and the chaff points obtained from two applications is computationally hard. Based on the experimental results, we confirm that the proposed approach provides higher security than inserting chaffs randomly without a significant degradation of the verification accuracy, and our implementation can be used for real applications.

• Korean Journal of Optics and Photonics
• /
• v.20 no.3
• /
• pp.143-147
• /
• 2009

We propose an asymmetrical 2.5 Gbps / 622 Mbps bidirectional optical subscriber network with Manchester coded downstream and NRZ (Non-Return-to-Zero) upstream remodulation. The proposed system has important characteristics in the optical network unit (ONU): it does not require a light source or the usual control circuits such as wavelength control and output power control, and it is possible to use a synchronization scheme between upstream and downstream data. We theoretically analyze BER(Bit Error Rate) performance of upstream data remodulated with Manchester coded downstream according to the types of NRZ downstream data and perform simulations with MATLAB. The BER performance and the receiver sensitivity have been improved by 3 dB by adjusting threshold levels compared to the conventional receiver. The results have shown the remodulation scheme with Manchester coded downstream could be a useful technology for asynchronous and asymmetric optical subscriber networks with low cost and simple structures.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.21 no.4
• /
• pp.984-995
• /
• 1996

Data errors according to the various noises caused in the satellite communication links are corrected by the Viterbi decoding algorithm which has extreme error correcting capability. In this paper, we designed and implemented a convolutional encoder and Viterbi decoder ASIC which is used to encode the input data at the transmit side and correct the errors of the received data at the receive side for use in the VSAT communication system. And this chip may be used in any BPSK, QPSK, or OQPSK transmission system. The ambiguity resolver corrects PSK modem ambiguities by delaying, interting, and/or exchanging code symbol to restore their original sequence and polarity. In case of previous decoding system, ambiguity state(AS) of data is resolved by external control logic and extra redundancy data are needed to resolve AS. But, by adopting decoder proposed in this paper, As of data is resolved automatically by internal logic of decoder in case of continuous mode, and by external As line withoug extra redudancy data in burst mode case. So, decoding parts are simple in continuous mode and transmission efficiency is increased in bust mode. The features of this chip are full duplex operation with independent transmit and receive control and clocks, start/stop inputs for use in burst mode systems, loopback function to verify encoder and decoder, and internal or external control to resolve ambinguity state. For verification of the function and performance of a fabricated ASIC chip, we equiped this chip in the Central and Remote Earth Station of VSAT system, and did the performance test using the commerical INTELSAT VII under the real satellite link environmens. The results of test were demonstrated the superiority of performance.

• Journal of Korea Multimedia Society
• /
• v.16 no.7
• /
• pp.841-851
• /
• 2013

The infectious information hiding system(IIHS) is proposed for secure distribution of high quality video contents by applying optimized watermark embedding and detection algorithms to video codecs. And the watermark as infectious information is transmitted while target video is displayed or edited by codecs. This paper proposes a fast and effective reversible watermarking and infectious information generation for IIHS. Our reversible watermarking scheme enables video decoder to control video quality and watermark strength actively for by adding control code and expiration date with the watermark. Also, we designed our scheme with low computational complexity to satisfy it's real-time processing in a video codec, and to prevent time or frame delay during watermark detection and video restoration, we embedded one watermark and one side information within a macro-block. Experimental results verify that our scheme satisfy real-time watermark embedding and detection and watermark error is 0% after reversible watermark detection. Finally, we conform that the quality of restored video contens is almost same with compressed video without watermarking algorithm.

• Journal of the Korea institute for structural maintenance and inspection
• /
• v.11 no.5
• /
• pp.171-180
• /
• 2007

The quality of ready-mixed concrete(henceforth abbreviated remicon) is influenced by various factors such as ingredient of material, difference of property, mixing ratio, mixing time, mixing error, conditioning of construction, method of curing and temperature, humidity time in transportation. These factors make it hard to confirm the quality of remicon till placing in site. As the quality control in field is very important to ensure the quality of building. Moreover in modern building production, the more important the inquiry of performance improvement, the more important the manufacture and the quality control of remicon. In this study, to examine and analyze the quality of remicon we used slump, air content and compressive strength in 7, 28 days as to remicon which placed during on year. As a result, we found that the slump and air content were satisfied with reference code and the compressive strength was more than the design standard strength so we concluded that the quality control of remicon was to be agreeable.

• Journal of Convergence for Information Technology
• /
• v.9 no.7
• /
• pp.25-32
• /
• 2019

This paper proposes the method of an in-vehicle gateway to reduce the reprogramming time for the ECU (Electronic Control Unit). In order to reduce the reprogramming time, the gateway must prohibit transmitting messages, that are not related to reprogramming, to the destination CAN network, and no ECU should diagnose the DTC(Diagnostic Trouble Code) that indicates CAN communication error caused by prohibiting CAN messages by the gateway. Moreover, STmin, which are the minimum time between two consecutive CAN messages, should be minimized. In order to do this, this paper proposes the method that uses the link control command specified in UDS(Unified Diagnostic Services) and hardware based gateway functionality that are supported by the latest MCU(Micro Controller Unit). The proposed method is developed using TC275 based embedded system, and its results are presented.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.25 no.11
• /
• pp.1581-1587
• /
• 2021

As embedded system are used widely and variously, multi-edge system, which multiple edges gather and perform complex operations together, is actively operating. In a multi-edge system, it often occurs that an abnormal operation at one edge is transferred to another edge or the entire system goes down. It is necessary to determine and control edge anomalies in order to prevent system down, but this can be a heavy burden on the resource-limited edge. As a solution to this, we use power consumption data to check the state of the edge device and transmit it based on a QRcode to check and control errors at the server. The architecture proposed in this paper is implemented using 'chip-whisperer' to measure the power consumption of the edge and 'Raspberry Pi 3' to implement the server. As a result, the proposed architecture server showed successful data transmission and error determination without additional load appearing at the edge.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.3
• /
• pp.185-197
• /
• 2001

Recently, the design method by VHDL coding and synthesis has been used widely. As the integration ratio increases, the amount design by VHDL at a time also increases so many coding errors occur in a design. Thus, lots of time and effort is dissipated to detect those coding errors. This paper proposed a method to verify the coding errors in VHDL behavioral-level designs. As the methodology, we chose the method to detect the coding error by applying the generated set of verifying patterns and comparing the responses from the error-free case(gold unit) and the real design. Thus, we proposed an algorithm to generate the verifying pattern set for the coding errors. Verifying pattern generation is peformed for each code and the coding errors are classified as two kind: condition errors and assignment errors. To generate the patterns, VHDL design is first converted into the corresponding CDFG(Control & Data Flow Graph) and the necessary information is extracted by searching the paths in CDFG. Path searching method consists of forward searching and backward searching from the site where it is assumed that coding error occurred. The proposed algorithm was implemented with C-language. We have applied the proposed algorithm to several example VHDL behavioral-level designs. From the results, all the patterns for all the considered coding errors in each design could be generated and all the coding errors were detectable. For the time to generate the verifying patterns, all the considered designed took less than 1 ［sec］ of CPU time in Pentium-II 400MHz environments. Consequently, the verification method proposed in this paper is expected to reduce the time and effort to verify the VHDL behavioral-level designs very much.