• Journal of Communications and Networks
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• v.11 no.3
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• pp.229-239
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• 2009

Orthogonal frequency division multiplexing (OFDM) has been adopted as a standard for various high data rate wireless communication systems due to the spectral bandwidth efficiency, robustness to frequency selective fading channels, etc. However, implementation of the OFDM system entails several difficulties. One of the major drawbacks is the high peak-to-average power ratio (PAPR), which results in intercarrier interference, high out-of-band radiation, and bit error rate performance degradation, mainly due to the nonlinearity of the high power amplifier. This paper reviews the conventional PAPR reduction schemes and their modifications for achieving the low computational complexity required for practical implementation in wireless communication systems.

• Journal of Electrical Engineering and Technology
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• v.7 no.2
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• pp.221-224
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• 2012

We propose a Readout Integrated Circuit (ROIC), which applies a fixed current bias sensing method to the input stage in order to simplify the circuit structure and the infrared sensor characteristic control. For the sample-and-hold stage to display and control a signal detected by the infrared sensor using a two-dimensional (2D) focal plane array, a differential delta sampling (DDS) circuit is proposed, which effectively removes the FPN. In addition, the output characteristic is improved to have wider bandwidth and higher gain by applying a two-stage variable gain amplifier (VGA). The output characteristic of the proposed device was 23.91 mV/$^{\circ}C$, and the linearity error rate was less than 0.22%. After checking the performance of the ROIC using HSPICE simulation, the chip was manufactured and measured using the SMIC 0.35 um standard CMOS process to confirm that the simulation results from the actual design are in good agreement with the measurement results.

• Journal of Power Electronics
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• v.13 no.6
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• pp.991-999
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• 2013

In this paper, a fast transient buck converter using hysteresis PWM control is presented. The proposed control method is based on hysteresis control of the capacitor C voltage. This offers a faster transient response to meet the challenges of the power supply requirements for fast dynamic input and load changes. It also provides better stability and solves the compensation problem of the error amplifier in conversional voltage PWM control. Finally, the steady-state and dynamic operation of the proposed control method are analyzed and verified by simulation and experimental results.

• Current Optics and Photonics
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• v.2 no.6
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• pp.519-524
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• 2018

We propose a transverse load sensor with reconfigurable measurement accuracy based on a microwave photonic filter in the $K_u$ band, incorporating a polarization-maintaining fiber Bragg grating. A prototype sensor with a reconfigurable measurement accuracy tuning range from 6.09 to 9.56 GHz/(N/mm), and corresponding minimal detectable load range from 0.0167 to 0.0263 N/mm, is experimentally demonstrated. The results illustrate that up to 40% manufacturing error in the grating length can be dynamically calibrated to the same corresponding measurement accuracy for the proposed transverse load sensor, by controlling the semiconductor optical amplifier's injection current in the range of 154 to 419 mA.

• Journal of IKEEE
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• v.24 no.4
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• pp.1162-1166
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• 2020

In this paper Low Drop-Out (LDO) regulator that improved load regulation characteristics due to the feedback detection structure. The proposed feedback sensing circuit is added between the output of the LDO's internal error amplifier and the input of the pass transistor to improve the regulation of the delta value coming into the output. It has a voltage value with improved load regulation characteristics than existing LDO regulator. The proposed LDO structure was analyzed in Samsung 0.13um process using Cadence's Virtuoso, Spectre simulator.

• Journal of information and communication convergence engineering
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• v.10 no.1
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• pp.85-90
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• 2012

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.12 s.91
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• pp.1184-1189
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• 2004

A new schematic of quadrature voltage controlled oscillator(QVCO) is designed and fabricated. To obtain quadrature characteristic and low phase noise simultaneously, two differential VCOs are forced to un in quadrature mode by using coupling amplifier with a source degeneration resistor, which is optimized to obtain quadrature accuracy with minimum phase noise degradation. The designed QVCO was fabricated in standard CMOS technology. The measured performance showed the phase noise of below -120 dBc/Hz at 1 MHEz frequency offset, tuning bandwidth of 210 MHz from 2.34 GHz to 2.55 GHz with a tuning voltage varying form 0 to 1.8 V Quadrature error of 0.5 degree and amplitude error of 0.2 dB was measured with conjunction with low-lF mixer. The fabricated QVCO requires 19 mA including 5 mA in the VCO core part fiom a 1.8 V supply.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.9
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• pp.4462-4466
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• 2013

In optical system, the signal and additive noise for statistical properties of a variety of ways to evaluate the performance of the system is essential for the optimization. In this paper, performance analysis of spectrum-sliced optical system in the optical pre-amplifier in the receiver the received signal by including the error limits for the bit that is, the bit error rate (BER: Bit Error Rate) required to maintain the average optical power represents the number of photons per bit is included in this paper to digital form, noticeable signal the receiver to calculate the sensitivity of the method for the calculation was performed. The general strength of the transmission of the modulated signal and digital signal transmission was required for the comparison of optical power. As shown in Figure 3, the general strength of the digital signal transmission system for transmitting a modulated signal compared with the case is improved by at least 10dB.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1749-1753
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• 2003

We proposed several systems for 1Giga bit Modem. The first, Binary ASK(Amplitude Shift Keying) system has a high speed shutter transmitter and no IF(Intermediate Frequency) receiver only by symbol synchronization. The advantage of proposed system is that circuitry is very simple without IF process. The disadvantage of proposed system are that line spectrum occurs interference to other channels, and enhancement to 4-level system is impossible due to its large SNR degradation. The second, Binary phase modulation system has a high speed shutter transmitter and IF-VCO(IF-Voltage Controlled Oscillator) control by base-band phase rotation. Polarity of shutter window is changed by the binary data. The window should be narrow same as above ASK. The advantage of proposed system is which error rate performance is superior. The disadvantage of proposed system are that Circuitry is more complex, narrow pull-in range of receiver caused by VCO and spectrum divergence by the non-linear amplifier. The third, 4-QAM(Quadrature Amplitude Modulation)system has a nyquist pulse transmitter and IF-VCO control by symbol clock. The advantage of proposed system are that signal frequency band is a half of 1GHz, reliable pull-in of VCO and possibility of double speed transmission(2Gbps) by keeping 1GHz frequency-band. The disadvantage of proposed system are that circuit complexity of pulse shaping and spectrum divergence by the non-linear amplifier.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.3
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• pp.292-299
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• 2015

An envelope elimination and restoration transmitter that uses a tri-level envelope encoding scheme is presented for improving the efficiency and linearity of the system. The proposed structure amplifies the same magnitude signal regardless of the input peak-to-average power ratio and reduces the quantization noise by spreading out the noise to the out-of-band frequency, resulting in the enhancement of power efficiency. An improved linearity is also obtained by providing a new timing mismatch calibration technique between the envelope and phase signal. Implementation in a 130 nm CMOS process, transmitter measurements on a 20-MHz long-term evolution input signal show an error vector magnitude of 3.7 % and an adjacent channel leakage ratio of 37.5 dBc at 2.13 GHz carrier frequency.