• 제목/요약/키워드: Error Recovery System

검색결과 179건 처리시간 0.028초

산업폐열 발전시스템 경제성분석 모듈 개발 및 신뢰성 최적화 (Development and Reliability Optimization of Economic Analysis Module for Power Generation System from Industrial Waste Heat Recovery)

  • 고아름;박성호;김준영;차재민
    • 에너지공학
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    • 제27권4호
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    • pp.50-63
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    • 2018
  • 화석연료의 무분별한 사용으로 인해 지구 온난화 및 환경오염 문제가 대두되고 있으며, 이에 따라 효율적인 에너지 활용을 위해 기존에 버려지는 폐열을 회수하는 기술에 대한 필요성이 커지고 있다. 산업폐열 발전 시장은 발전효율을 높일 수 있다는 장점으로 인해 연평균 5% 성장하고 있다. 고효율 폐열발전시스템 설계를 위해 열원별 조건에 따른 발전 기술별 경제성을 평가할 수 있는 프로그램 개발이 필요하다. 따라서 본 연구에서는 산업폐열 발전시스템에 최적화된 경제성분석 모듈 개발을 위해 균등화 전력원가를 산출하는 모듈을 개발하고 NETL의 경제성분석 사례를 바탕으로 시스템의 신뢰도를 검증하였다. 검증 결과, 오차율은 약 6~7%로 사업 타당성 평가를 위한 정확도를 만족하였으나, 신뢰성 향상을 위해 NETL에서 사용하는 균등화 방법론을 적용하여 알고리즘을 개선하였고 이에 따라 오차율은 1% 미만으로 신뢰도가 향상되었다.

MPEG-2 동영상 표준방식에 대한 채널 오차의 검출 및 은폐 기법 (Channel Error Detwction and Concealment Technqiues for the MPEG-2 Video Standard)

  • 김종원;박종욱;이상욱
    • 한국통신학회논문지
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    • 제21권10호
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    • pp.2563-2578
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    • 1996
  • In this paper, channel error characteristics are investigated to alleviate the channel error propagation problem of the digital TV transmission systems. First, error propagation problems, which are mainly caused by the inter-frame dependancy and variable length coding of the MPEG-2 baseline encoder, are intensively analyzed. Next, existing channel resilient schemes are systematically classified into two kinds of schemes; one for the encoder and the other for the decoder. By comparing the performance and implementation cost, the encoder side schemes, such as error localization, layered coding, error resilience bit stream generation techniques, are described in this paper. Also, in an effort to consider the parcticality of the real transmission situation, an efficient error detection scheme for a decoder system is proposed by employing a priori information of the bit stream syntas, checking the encoding conditions at the encoder stage, and exploiting the statistics of the image itself. Finally, subsequent error concealment technique based on the DCT coefficient recovery algorithm is adopted to evaluate the performance of the proposed error resilience technique. The computer simulation results show that the quality of the received image is significantly improved when the bit error rate is as high as 10$^{-5}$ .

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Consistency preservation techniques for Location Register System in Mobile Networks

  • Kim, Jang-Hwan
    • International Journal of Internet, Broadcasting and Communication
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    • 제12권2호
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    • pp.144-149
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    • 2020
  • A database called Home Location Register(HLR) plays a major role in location management in mobile cellular networks. The objectives of this paper are to identify the problems of the current HLR system through rigorous analysis, to suggest solutions to them. The current HLR backup method is a process of simply writing the changed memory SLD block to disk, which has a problem in maintaining database consistency. Since information change and backup are performed separately by separate processes, there is a risk of information inconsistency when an error restart occurs. To solve this problem, a transaction concept was introduced for subscriber-related operation functions and a recovery method through logging and checkpointing was introduced. The subscriber related functions of tasks terminated normally by the suggested process are recovered with consistency even after system restarts. Performance is also not affected seriously because disk tasks for log occur with only subscriber related functions.

다중 로보트 시스템의 작업 스케쥴링 및 성능 평가 (Job scheduling and performance evaluation of MRS(Multi Robot System))

  • 이기동;조혜경;이범희;고명삼
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 1990년도 한국자동제어학술회의논문집(국내학술편); KOEX, Seoul; 26-27 Oct. 1990
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    • pp.423-428
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    • 1990
  • A mixed IP formulation is presented which concurrently routes and sequences the tasks on the MRS, reflecting the flexible characteristics. As a preliminary work for the performance evaluation of the MRS, a two robot system working on independent tasks is studied. Models for three types of the system capable of simple error recovery function are established using queueing model, and performances are evaluated and analysed.

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Compensation Technique for Current Sensorless Digital Control of Bridgeless PFC Converter under Critical Conduction Mode

  • Kim, Tae-Hun;Lee, Woo-Cheol
    • Journal of Electrical Engineering and Technology
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    • 제13권6호
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    • pp.2310-2318
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    • 2018
  • Critical conduction mode (CRM) operation is more efficient than continuous conduction mode (CCM) operation at low power levels because of the valley switching of switches and elimination of the reverse recovery losses of boost diodes. When using a sensorless digital control method, an error occurs between the actual and the estimated current. Because of the error, it operates as CCM or discontinuous conduction mode (DCM) during CRM operation and also has an adverse effect on THD of input current. In this paper, a current sensorless technique is presented in an inverter system using a bridgeless boosted power factor correction converter, and a compensation method is proposed to reduce CRM calculation error. The validity of the proposed method is verified by simulation and experiment.

라이시안 페이딩 채널에서 위상 추정 에러가 있는 DS-CDMA BPSK/QPSK 신호의 성능 개선 (Performance Improvement of DS-CDMA BPSK/QPSK in the Presence of Phase Estimation Error in the Rician Fading Channel)

  • 전준수;강희조
    • 한국전자파학회논문지
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    • 제11권2호
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    • pp.252-258
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    • 2000
  • 본 논문에서는 다중경로 라이시안 페이딩 채널에서 DS-CDMA 시스템의 반송파 회복 선호가 불안전할 때 BPSK와 QPSK의 에러성능을 개선한다. 이 경우에 반송파 위상 추정 에러가 있는 환경에서 라이시안 페이딩을 극복하기 위하여 MRC(Maximal Ratio Combining) 다이버시티와 컨벌루션 부호화 기법을 사용하여 시스템 성능 분석을 하였다. 분석의 결과 MRC 다아버시티와 컨벌루션 부호를 적절히 사용하면 위상 에러에 의한 성능 저하률 상당히 줄 일 수 있다는 것을 알 수 있었다.

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2차원 광부호분할 다중접속 시스템에 의한 영상의 병렬 전송과 복원법 (Parallel Transmission and Recovery Methods of Images Using the Two Dimensional Fiber-Optic Code-Division Multiple-Access System)

  • 이태훈;박영재;서익수;박진배
    • 대한전기학회논문지:시스템및제어부문D
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    • 제49권12호
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    • pp.683-689
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    • 2000
  • Two-dimensional(2-D) fiber-optic code-division multiple-access(FO-CDMA) system utilizes the optical orthogonal signature pattern code(OOSPC) to encode and decode 2-D data. Encoded 2-D data are spatially multiplexed and transmitted through an image fiber and receiver recovers the intended data by means of thresholding process. OOSPC's construction methods based on expansion of the optical orthogonal code, which is used in one-dimensional(1-D) FO-CDMA system, are introduced. Each OOSPC's performances are compared by using the bit error rate(BER) of interfering OOSPC's of other users. From the results we verify that a balanced incomplete block design(BIBD) construction has the best performance among other mehtods. We also propose a decomposed bit-plane method for parallel transmission and recovery of 256 gray-scale images using OOSPC's constructed by the BIBD method. The simulation result encourages the feasibility of parallel transmission and recovery of multiuser's images.

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Design and Implementation of Open-Loop Clock Recovery Circuit for 39.8 Gb/s and 42.8 Gb/s Dual-Mode Operation

  • Lim, Sang-Kyu;Cho, Hyun-Woo;Shin, Jong-Yoon;Ko, Je-Soo
    • ETRI Journal
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    • 제30권2호
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    • pp.268-274
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    • 2008
  • This paper proposes an open-loop clock recovery circuit (CRC) using two high-Q dielectric resonator (DR) filters for 39.8 Gb/s and 42.8 Gb/s dual-mode operation. The DR filters are fabricated to obtain high Q-values of approximately 950 at the 40 GHz band and to suppress spurious resonant modes up to 45 GHz. The CRC is implemented in a compact module by integrating the DR filters with other circuits in the CRC. The peak-to-peak and RMS jitter values of the clock signals recovered from 39.8 Gb/s and 42.8 Gb/s pseudo-random binary sequence (PRBS) data with a word length of $2^{31}-1$ are less than 2.0 ps and 0.3 ps, respectively. The peak-to-peak amplitudes of the recovered clocks are quite stable and within the range of 2.5 V to 2.7 V, even when the input data signals vary from 150 mV to 500 mV. Error-free operation of the 40 Gb/s-class optical receiver with the dual-mode CRC is confirmed at both 39.8 Gb/s and 42.8 Gb/s data rates.

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소프트 에러 발생 시 자동 복구하는 이중 코어 지연 락스텝 프로세서의 설계 (Design of a Delayed Dual-Core Lock-Step Processor with Automatic Recovery in Soft Errors)

  • 김주호;양성현;이성수
    • 전기전자학회논문지
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    • 제27권4호
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    • pp.683-686
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    • 2023
  • 본 논문에서는 차량 전자 시스템에서 소프트 에러와 공통 고장에 대응하기 위해 두 개의 코어를 지연 동작시킨 후 그 결과를 비교하는 D-DCLS(Delayed Dual Core Lock-Step) 프로세서를 설계하였다. D-DCLS는 어느 코어에서 에러가 발생했는지 알 수 없기 때문에 각 코어를 에러가 발생하기 이전 시점으로 되돌려야 하는데 파이프라인 스테이지 상의 모든 중간 계산값을 되돌리기 위해서는 복잡한 하드웨어 수정이 필요하다. 본 논문에서는 이를 쉽게 구현하기 위해 분기 명령어가 실행될 때마다 모든 레지스터 값을 버퍼에 저장해 두었다가 에러가 발생하면 저장된 레지스터 값을 복구한 후 'BX LR' 명령어를 수행하여 해당 분기 시점으로 자동 복구하도록 하였다. 제안하는 D-DCLS 프로세서를 Verilog HDL로 설계하여 에러가 감지되었을 때 자동으로 복구한 후 정상 동작하는 것을 확인하였다.

Sensorless Control of Non-salient Permanent Magnet Synchronous Motor Drives using Rotor Position Tracking PI Controller

  • Lee Jong-Kun;Seok Jul-Ki
    • KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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    • 제5B권2호
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    • pp.189-195
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    • 2005
  • This paper presents a new velocity estimation strategy for a non-salient permanent magnet synchronous motor drive without high frequency signal injection or special PWM pattern. This approach is based on the d-axis current regulator output voltage of the drive system, which contains the rotor position error information. The rotor velocity can be estimated through a rotor position tracking PI controller that controls the position error at zero. For zero and low speed operation, the PI gain of the rotor position tracking controller has a variable structure according to the estimated rotor velocity. Then, at zero speed, the rotor position and velocity have sluggish dynamics because the varying gains are very low in this region. In order to boost the bandwidth of the PI controller during zero speed, the loop recovery technique is applied to the control system. The PI tuning formulas are also derived by analyzing this control system by frequency domain specifications such as phase margin and bandwidth assignment.