• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.1
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• pp.65-74
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• 1989

This paperr presetns the Direct Decoding Method for binary BCH codes which can find the error locattion number directly from the syndrome without calculating the error locator polynomical. Also in this paper, the triple and quadruple error correcting BCH decoder are designed using this method. As an example, the triple error correcting (63.45) BCH decoder is implemented with TTL ICs. It is shown from our results that this decoder can be implemented with relatively simple hardware.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.10
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• pp.1559-1562
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• 2022

As electronic devices technology scales down into the deep-submicron to achieve high-density, low power and high performance integrated circuits, multiple bit upsets by soft errors have become a major threat to on-chip memory systems. To address the soft error problem, single error correction, double error detection and double adjacent error correction (SEC-DED-DAEC) codes have been recently proposed. But these codes do not troubleshoot mis-correction problem. We propose the SEC-DED_DAEC code with without mis-correction. The decoder for proposed code is implemented as hardware and verified. The results show that there is no mis-correction in the proposed codes and the decoder can be employed on-chip memory system.

• Journal of Communications and Networks
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• v.17 no.4
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• pp.351-361
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• 2015

In this paper, a new decoding scheme is proposed to improve the error correcting performance of low-density parity-check (LDPC) codes in high signal-to-noise ratio (SNR) region by using post-processing. It behaves as follows: First, a conventional LDPC decoding is applied to received LDPC codewords one by one. Then, we count the number of word errors in a predetermined number of decoded codewords. If there is no word error, nothing needs to be done and we can move to the next group of codewords with no delay. Otherwise, we perform a proper post-processing which produces a new soft-valued codeword (this will be fully explained in the main body of this paper) and then apply the conventional LDPC decoding to it again to recover the unsuccessfully decoded codewords. For the proposed decoding scheme, we adopt a simple product code structure which contains LDPC codes and simple algebraic codes as its horizontal and vertical codes, respectively. The decoding capability of the proposed decoding scheme is defined and analyzed using the parity-check matrices of vertical codes and, especially, the combined-decodability is derived for the case of single parity-check (SPC) codes and Hamming codes used as vertical codes. It is also shown that the proposed decoding scheme achieves much better error correcting capability in high SNR region with little additional decoding complexity, compared with the conventional LDPC decoding scheme.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.1 no.1
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• pp.66-78
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• 1991

In this paper, this paper, the stream cipher systems and the error propagation are analyzed. During the ciphertext transmission. for the error control of errors occurred in the channel, the DSEC(31, 27) RS codes will be used for bothe internal and external error controls for the self-synchromizing cipher system with ciphertext feedback.

• Honam Mathematical Journal
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• v.30 no.1
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• pp.33-45
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• 2008

Lee weight is more appropriate for some practical situations than Hamming weight as it takes into account magnitude of each digit of the word. In this paper, we obtain a sufficient condition over the number of parity check digits for codes correcting random errors and simultaneously detecting burst errors with Lee weight consideration.

• ETRI Journal
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• v.37 no.1
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• pp.54-60
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• 2015

The use of serial concatenated codes is an effective technique for alleviating the error floor phenomenon of low-density parity-check (LDPC) codes. An enhanced sum-product algorithm (SPA) for LDPC codes, which is suitable for serial concatenated codes, is proposed in this paper. The proposed algorithm minimizes the number of errors by using the failed check nodes (FCNs) in LDPC decoding. Hence, the error-correcting capability of the serial concatenated code can be improved. The number of FCNs is simply obtained by the syndrome test, which is performed during the SPA. Hence, the decoding procedure of the proposed algorithm is similar to that of the conventional algorithm. The error performance of the proposed algorithm is analyzed and compared with that of the conventional algorithm. As a result, a gain of 1.4 dB can be obtained by the proposed algorithm at a bit error rate of $10^{-8}$. In addition, the error performance of the proposed algorithm with just 30 iterations is shown to be superior to that of the conventional algorithm with 100 iterations.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2018.11a
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• pp.11-14
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• 2018

The aim of this study is to rectify the misclassified image features and enhance the performance of image classification tasks by incorporating a channel- coding technique, widely used in telecommunication. Specifically, the proposed algorithm employs the error - correcting mechanism of convolutional coding combined with the convolutional neural networks (CNNs) that are the state - of- the- arts image classifier s. We develop an encoder and a decoder to employ the error - correcting capability of the convolutional coding. In the encoder, the label values of the image data are converted to convolutional codes that are used as target outputs of the CNN, and the network is trained to minimize the Euclidean distance between the target output codes and the actual output codes. In order to correct misclassified features, the outputs of the network are decoded through the trellis structure with Viterbi algorithm before determining the final prediction. This paper demonstrates that the proposed architecture advances the performance of the neural networks compared to the traditional one- hot encoding method.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1983.10a
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• pp.73-76
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• 1983

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.2
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• pp.86-91
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• 2014

Holographic data storage (HDS) has a number of advantages, including a high transmission rate through the use of a charge coupled device array for reading two-dimensional (2D) pixel image data, and a high density capacity. HDS also has disadvantages, including 2d intersymbol interference by neighboring pixels and interpage interference by multiple pages stored in the same holographic volume. These problems can be eliminated by modulation codes. We propose a 7/9 error-correcting modulation code that exploits a Viterbi-trellis algorithm and has a code rate larger (about 0.778) than that of the conventional 6/8 balanced modulation code. We show improved performance of the bit error rate with the proposed scheme compared to that of the simple 7/9 code without the trellis scheme and the 6/8 balanced modulation code.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1986.10a
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• pp.79-82
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• 1986

For the purpose of error correcting, a concatenated coding system has been proposed by cascading two codes-(7, 3) Reed-Solomon and (2, 1, 6) convolutional codes. As a result of the result of the computer simulation and the experiment, the (98.21) concatenated code has been show to be able to correct 12 randome error and 16 bust errors. When the channel error is about 1.2x10, this system indicats most efficient.