• Title/Summary/Keyword: Equivalent Elmore Delay

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A Delay Estimation Method using Reduced Model of RLC Interconnects (RLC 연결선의 축소모형을 이용한 지연시간 계산방법)

  • Jung Mun-Sung;Kim Ki-Young;Kim Seok-Yoon
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.54 no.8
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    • pp.350-354
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    • 2005
  • This paper proposes a new method for delay time calculation in RLC interconnects. This method is simple, but precise. The proposed method can calculate delay time of RLC interconnects by simple numerical formula calculation without complex moment calculation using reduced model in RLC interconnects. The results using the proposed method for RLC circuits show that average relative error is within $10\%$ in comparison with HSPICE simulation results.

RC Tree Delay Estimation (RC tree의 지연시간 예측)

  • 유승주;최기영
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.32A no.12
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    • pp.209-219
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    • 1995
  • As a new algorithm for RC tree delay estimation, we propose a $\tau$-model of the driver and a moment propagation method. The $\tau$-model represents the driver as a Thevenin equivalent circuit which has a one-time-constant voltage source and a linear resistor. The new driver model estimates the input voltage waveform applied to the RC more accurately than the k-factor model or the 2-piece waveform model. Compared with Elmore method, which is a lst-order approximation, the moment propagation method, which uses $\pi$-model loads to calculate the moments of the voltage waveform on each node of RC trees, gives more accurate results by performing higher-order approximations with the same simple tree walking algorithm. In addition, for the instability problem which is common to all the approximation methods using the moment matching technique, we propose a heuristic method which guarantees a stable and accureate 2nd order approximation. The proposed driver model and the moment propagation method give an accureacy close to SPICE results and more than 1000 times speedup over circuit level simulations for RC trees and FPGA interconnects in which the interconnect delay is dominant.

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