• Journal of KIISE:Software and Applications
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• v.30 no.7_8
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• pp.642-648
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• 2003

In this paper, we are interested in checking equivalence of FSMs(finite state machines). Two FSMs are equivalent if and only if their responses are always equal with each other with respect to the same external stimuli. Equivalence checking FSMs makes complicated FSM be substituted for simpler one, if they are equivalent. We can also determine the system satisfies the requirements, if they are all written in FSMs. In this paper, we regard equivalence checking problem as model checking one. For doing so, we construct the product model $M ={M_A} {\beta}{M_B} from two FSMs ${M_A} and {M_B}$. And we also get the temporal logic formula ${\Phi}$ from the equivalence checking definition. Then, we can check with model checker whether if satisfies ${\Phi}$, written $M= {.\Phi}$. Two FSMs are equivalent, if $M= {.\Phi}$ Otherwise, it is not equivalent. In that case, model checker generates counterexamples which explain why FSMs are not equivalent. In summary, we solve the equivalence checking problem with model checking techniques. As a result of applying to several examples, we have many satisfiable results.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.960-964
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• 2004

During system resource improvement process that based on Object-Oriented technology could be affect to the continuous system performance if lack appropriate management and control objects mechanism. This paper proposes a methodology to support continuous system performance and its stability. The adoption is based on Java Container Framework and Collections Framework for object collection. Also includes Software Engineering, Object Migration and Multiple Class Loaders mechanism accommodate to construct Continuous Migration Container (CMC). CMC is a runtime environment provides interfaces for management and control to support upgrading object process. Upgrade object methodology of CMC can be divided into two phase are object equivalence checking and object migration process. Object equivalence checking include object behavior verification and functional conformance verification before object migration process. In addition, CMC use Multiple Class Loaders mechanism to support reload effected classes instead of state transfer in migration process while upgrading object. These operations are crucial for system stability and enhancement efficiency.

• The KIPS Transactions:PartD
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• v.14D no.6
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• pp.633-640
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• 2007

As the embedded systems closely related with our living become complex by interoperating each other via internet, the safety issue of embedded systems begins to appear For checking safety properties of the system interactions, it is necessary to describe the system behaviors in formal methods and provide a systematic safety analysis technique. In this research, the behaviors of an embedded system are described by Labeled Transition Systems(LTS) and its safety properties are checked on the system model. For enhancing the existing compositional safety analysis technique, we perform the safety analysis techniques by checking the behavioral equivalence of the reduced model and a property model after reducing the system model in the viewpoint of the property.

• Korean Journal of Mathematics
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• v.28 no.2
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• pp.285-294
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• 2020

We study the complementary information set codes (for short, CIS codes) over 𝔽₄. They are strongly connected to correlation-immune functions over 𝔽₄. Also the class of CIS codes includes the self-dual codes. We find a construction method of CIS codes over 𝔽₄ and a criterion for checking equivalence of CIS codes over 𝔽₄. We complete the classification of all inequivalent CIS codes of length up to 8 over 𝔽₄.

• Communications for Statistical Applications and Methods
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• v.13 no.3
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• pp.777-786
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• 2006

Two factorial designs with quantitative factors are called geometrically equivalent if the design matrix of one can be transformed into the design matrix of the other by row and column permutations, and reversal of symbol order in one or more columns. Clark and Dean (2001) gave a sufficient and necessary condition (which we call the 'gCD condition') for two symmetric factorial designs with quantitative factors to be geometrically equivalent. This condition is based on the absolute value of the Euclidean(or Hamming) distance between pairs of design points. In this paper we extend the gCD condition to asymmetric designs. In addition, a modified algorithm is applied for checking the equivalence of two designs.

• Proceedings of the Korean Information Science Society Conference
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• 2008.06b
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• pp.568-571
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• 2008

하드웨어 개발에 있어서 데이터의 신속한 처리와 공정의 저렴한 비용을 위해 회로의 많은 부분이 게이트 레벨에서 구현된다. 기능 검사는 하드웨어 개발에 있어서 설계의 기능을 분석하는 중요한 설계 흐름이다. 기존의 기능 검사는 사용자의 요구에 의해 하드웨어 시스템이 복잡해지고 개발 주기가 점점 빨라지는 시장의 특성으로 인해 설계자에게 시간적 경제적인 부담감을 준다. 본 연구에서는 설계자에게 가중되는 부담을 극복하고 보다 효율적인 기능 검사를 위해 모델 체킹을 동치성 검사에 적용하는 방법을 제안하고자 한다.

• Proceedings of the Korean Information Science Society Conference
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• 2007.06b
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• pp.354-357
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• 2007

하드웨어 개발에 있어서 데이터의 신속한 처리와 공정의 저렴한 비용을 위해 회로의 많은 부분이 게이트 레벨에서 구현된다. 기능 검사는 하드웨어 개발에 있어서 설계의 기능을 분석하는 중요한 설계 흐름이다. 기존의 기능 검사는 사용자의 요구에 의해 하드웨어 시스템이 복잡해지고 개발 주기가 점점 빨라지는 시장의 특성으로 인해 설계자에게 시간적 경제적인 부담감을 준다. 본 연구에서는 설계자에게 가중되는 부담을 극복하고 보다 효율적인 기능 검사를 위해 모델 체킹을 동치성 검사에 적용하는 방법을 제안하고자 한다.

• Proceedings of the Korean Information Science Society Conference
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• 2003.04c
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• pp.37-39
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• 2003

본 연구에서는 만족성 검사기를 이용하여 두 유한 상태 기계의 행위가 동치인지를 검사한다. 기존의 동치 검사는 대부분 BDD를 기반으로 했었기 때문에 변수 순서 배열 및 내부 BDD노드 폭발 문제에 시달렸었다. 하지만 여기서는 BDD대신 명제 논리를 이용하기 때문에 위와 같은 문제점을 피할 수 있다. 하지만 논리식을 만족성 검사기의 입력 형태인 논리곱 정규형으로 변환하는 과정에서 절의 3기는 식의 크기에 지수적으로 증가하였다.

• Proceedings of the Korean Information Science Society Conference
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• 2002.04b
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• pp.427-429
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• 2002

본 연구에서는 상태도를 평탄화 하는 대신에, 띠러 기계가 동시에 수행하는 병행 기계로 상태도를 표현한 후 ROBDD를 이 용하여 상태도의 동치 여 부를 기호적으로 검사하고자 한다. 상태도가 기능적으로 동치라는 것은, 두 상태도는 같은 함수를 구현하고 있다는 것과 같다. 이 것은 로든 입력 이벤트에 대하여 두 상태도의 반응이 항상동일 한지를 판정함으로써 가능하다. 즉 상태도의 동치 검사는, 입력 이벤트가 같은 상태들의 집합이 모든 입력 에 대 해서 출력 이 같은 상태들인가라는 문제로 축소된다.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.6
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• pp.608-619
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• 2000

In this paper, we give a formal semantics for Statechart via a translation into Algebra of Communicating Shared Hesources(ACSR). Statechart is a very rich graphical specification language, which is suitable to specify complicated reactive systems. However, the incorporation of graph into specification and rich syntax makes Statechart semantics very complicated and ambiguous. Thus, it is very difficult to verify the correctness of Statechart specifications. Also, we propose the formal verification method for Statechart specifications by showing equivalence relation between two Statechart specifications. This makes it possible to combine the advantages of a graphical language with the rigor of process algebra.