• Journal of Advanced Marine Engineering and Technology
• /
• 제37권4호
• /
• pp.351-357
• /
• 2013

플립칩 패키징에서 언더필 공정은 칩과 기판 사이를 에폭시로 채워서 본딩하는 공정으로 제품의 신뢰성 향상을 위해 수행되어 진다. 이 언더필 공정은 모세관 현상에 의해서 이루어지는데 유체의 계면과 범프의 배열이 계면 운동에 미치는 영향으로 인하여 공정 중 예기치 않은 공기층을 형성하게 된다. 본 연구에서는 모세관 언더필 유동에서 나타나는 비정상 계면 유동을 가시화하여 범프 배열에 따른 레이싱 효과와 계면의 병합 현상에 대하여 고찰하였다. 그 결과, 플립칩 내부의 범프가 고밀도일수록 유체의 흐름방향과 수직방향의 유동이 더욱 활발하게 진행되어 더 많은 공기층이 형성되었으며, 엇갈린 배열일 경우 직각 배열에 비해 이러한 현상이 더 지배적으로 나타난다.

• ETRI Journal
• /
• 제46권2호
• /
• pp.347-359
• /
• 2024

A simultaneous transfer and bonding (SITRAB) process using areal laser irradiation is introduced for high-yield and cost-effective production of mini- or micro-light-emitting diode (LED) display panels. SITRAB materials are special epoxy-based solvent-free pastes. Three types of pot life are studied to obtain a convenient SITRAB process: Room temperature pot life (RPL), stage pot life (SPL), and laser pot life (LPL). In this study, the RPL was found to be 1.2 times the starting viscosity at 25℃, and the SPL was defined as the time the solder can be wetted by the SITRAB paste at given stage temperatures of 80℃, 90℃, and 100℃. The LPL, on the other hand, was referred to as the number of areal laser irradiations for the tiling process for red, green, and blue LEDs at the given stage temperatures. The process windows of SPL and LPL were identified based on their critical time and conversion requirements for good solder wetting. The measured RPL and SPL at the stage temperature of 80℃ were 6 days and 8 h, respectively, and the LPL was more than six at these stage temperatures.

• Tribology and Lubricants
• /
• 제28권4호
• /
• pp.173-177
• /
• 2012

We used contact resonance force microscopy (CRFM) technique to determine the quantitative elastic properties of multiple materials integrated on the sub micrometer scale. The CRFM approach measures the frequencies of an AFM cantilever's first two flexural resonances while in contact with a material. The plain strain modulus of an unknown or test material can be obtained by comparing the resonant spectrum of the test material to that of a reference material. In this study we examined the following bumping materials for flip chip by using copper electrode as a reference material: NiP, Solder (Sn-Au-Cu alloy) and under filled epoxy. Data were analyzed by conventional beam dynamics and contact dynamics. The results showed a good agreement (~15% difference) with corresponding values determined by nanoindentaion. These results provide insight into the use of CRFM methods to attain reliable and accurate measurements of elastic properties of materials on the nanoscale.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
• /
• pp.205-208
• /
• 2001

Steady state and transient thermal analysis has been done by a finite element method in a diode of 12kV blocking voltage for microwave oven. The diode was fabricated by soldering ten pieces of 1200V diodes in series, capping a dummy wafer at the far end of diode series, and finally copper wire bonded for building anode and cathode terminal. In order to achieve high voltage and reliability, the edge of each diode was beveled and passivated by resin and epoxy with a thickness of $25{\mu}m$ and $3700{\mu}m$, respectively. The chip size, thickness and material properties were very important factor for high voltage diode package. And also, thermal stress value was highest in the edge of diode and solder. So, design of edge in silicon was very important to thermal stress.

• 한국표면공학회지
• /
• 제32권6호
• /
• pp.647-657
• /
• 1999

Due to the inherently poor adhesion strength of Cu-based leadframe/EMC (Epoxy Molding Compound) interface, popcorn cracking of thin plastic packages frequently occurs during the solder reflow process. In the present work, in order to enhance the adhesion strength of Cu-based leadframe/EMC interface, black-oxide layer was formed on the leadframe surface by chemical oxidation of leadframe, and then oxidized leadframe sheets were molded with EMC and machined to form SDCB (Sandwiched Double-Cantilever Beam) and SBN (Sandwiched Brazil-Nut) specimens. SDCB and SBN specimens were designed to measure the adhesion strength between leadframe and EMC in terms of critical energy-release rate under quasi-Mode I ($G_{IC}$ ) and mixed Mode loading ($G_{C}$ /) conditions, respectively. Results showed that black-oxide treatment of Cu-based leadframe initially introduced pebble-like X$C_2$O crystals with smooth facets on its surface, and after the full growth of $Cu_2$O layer, acicular CuO crystals were formed atop of the $Cu_2$O layer. According to the result of SDCB test, $Cu_2$O crystals on the leadframe surface did not increase ($G_{IC}$), however, acicular CuO crystals on the $Cu_2$O layer enhanced $G_{IC}$ considerably. The main reason for the adhesion improvement seems to be associated with the adhesion of CuO to EMC by mechanical interlocking mechanism. On the other hand, as the Mode II component increased, $G_{C}$ was increased, and when the phase angle was -34$^{\circ}$, crack Kinking into EMC was occured.d.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
• /
• pp.164-165
• /
• 2008

현재의 소자간 연결을 위해 사용되는 금속배선 PCB의 한계로 인해 보다 고속/대용량의 광PCB가 크게 각광받고 있다. 본 논문에서는 광PCB와 소자간의 전기적 연결을 위해 사용되는 솔더 범프를 전도성 에폭시를 사용하여 마이크로 머시닝 공정을 통해 구현하고 제작된 솔더 범프의 I-V 특성을 살펴보았다. 제작된 100 um $\times$ 100 um $\times$ 25 um 와 300 um $\times$ 300 um $\times$ 25 um 의 샘플에서 각각 30 m$\Omega$과 90m$\Omega$의 전기저항을 얻을 수 있었다. 이를 통해 향후 센서및 엑츄에이터 시스템과 광 MEMS 등의 여러 분야에서 전도성 에폭시 솔더 범프를 이용하여 우수한 성능의 플립칩 본딩을 구현할 수 있을 것이다.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2001년도 추계학술대회 논문집
• /
• pp.205-208
• /
• 2001

Steady state and transient thermal analysis has been done by a finite element method in a diode of 12kV blocking voltage for microwave oven. The diode was fabricated by soldering ten pieces of 1200V diodes in series, capping a dummy wafer at the far end of diode series, and finally copper wire bonded for building anode and cathode terminal. In order to achieve high voltage and reliability, the edge of each diode was beveled and passivated by resin and epoxy with a thickness of 25$\mu\textrm{m}$ and 3,700$\mu\textrm{m}$, respectively. The chip size, thickness and material properties were very important factor for high voltage diode package. And also, thermal stress value was highest in the edge of diode and solder. So, design of edge in silicon was very important to thermal stress.

• 마이크로전자및패키징학회지
• /
• 제16권4호
• /
• pp.23-28
• /
• 2009

Si 기판의 캐비티 형성이 불필요한 웨이퍼-레벨 MEMS capping 공정을 연구하였다. 4인치 Si 웨이퍼에 Ni 캡을 전기도금으로 형성하고 Ni 캡 rim을 Si 하부기판의 Cu rim에 에폭시 본딩한 후, SnBi debonding 층을 이용하여 상부기판을 Ni 캡 구조물로부터 debonding 하였다. 진공증착법으로 형성한 SnBi debonding 층은 Bi와 Sn 사이의 심한 증기압 차이에 의해 Bi/Sn의 2층 구조로 이루어져 있었다. SnBi 증착 층을 $150^{\circ}C$에서 15초 이상 유지시에는 Sn과 Bi 사이의 상호 확산에 의해 eutectic 상과 Bi-rich $\beta$상으로 이루어진 SnBi 합금이 형성되었다. $150^{\circ}C$에서 유지시 SnBi의 용융에 의해 Si 기판과 Ni 캡 구조물 사이의 debonding이 가능하였다.